DaVinci EMAC is present on TI AM35xx SoCs (ARMv7) which run with D-Cache
enabled by default. So we have to take care and flush/invalidate the
cache before/after the DMA operations.
Please note that the receive buffer alignment to 32 byte boundary comes
from the old driver version I don't know if i
Hi Andy,
On 12.11.2011 02:11, Andy Fleming wrote:
>> DaVinci EMAC is present on TI AM35xx SoCs (ARMv7) which run with D-Cache
>> enabled by default. So we have to take care and flush/invalidate the
>> cache before/after the DMA operations.
>>
>> Please note that the receive buffer alignment to 32
On Thu, Nov 10, 2011 at 6:39 PM, Ilya Yanok wrote:
> DaVinci EMAC is present on TI AM35xx SoCs (ARMv7) which run with D-Cache
> enabled by default. So we have to take care and flush/invalidate the
> cache before/after the DMA operations.
>
> Please note that the receive buffer alignment to 32 byte
DaVinci EMAC is present on TI AM35xx SoCs (ARMv7) which run with D-Cache
enabled by default. So we have to take care and flush/invalidate the
cache before/after the DMA operations.
Please note that the receive buffer alignment to 32 byte boundary comes
from the old driver version I don't know if i
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