On Sat, Dec 19, 2015 at 10:52 AM, Simon Glass wrote:
> On 11 December 2015 at 03:55, Bin Meng wrote:
>> This adds microcode blobs created from Intel FSP package for the
>> Chief River platform. They are for all the Ivy Bridge steppings:
>> 306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), exc
On 11 December 2015 at 03:55, Bin Meng wrote:
> This adds microcode blobs created from Intel FSP package for the
> Chief River platform. They are for all the Ivy Bridge steppings:
> 306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the
> 306a9 which is already in the U-Boot tree.
>
> Si
This adds microcode blobs created from Intel FSP package for the
Chief River platform. They are for all the Ivy Bridge steppings:
306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the
306a9 which is already in the U-Boot tree.
Signed-off-by: Bin Meng
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arch/x86/dts/microcode/m12306
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