Hi Anup,
On Thu, Dec 6, 2018 at 11:37 AM Anup Patel wrote:
>
> Hi Bin,
>
> On Tue, Nov 13, 2018 at 1:47 PM Bin Meng wrote:
> >
> > This adds DM drivers to support RISC-V CPU and timer.
> >
> > The U-Boot RISC-V SBI support is still working in progress.
> > Some patches in this series like adding
Hi Bin,
On Tue, Nov 13, 2018 at 1:47 PM Bin Meng wrote:
>
> This adds DM drivers to support RISC-V CPU and timer.
>
> The U-Boot RISC-V SBI support is still working in progress.
> Some patches in this series like adding CSR numbers, exception
> numbers, are prerequisites for the SBI implementatio
Hi Anup,
On Mon, Dec 3, 2018 at 3:59 PM Anup Patel wrote:
>
> On Tue, Nov 13, 2018 at 1:47 PM Bin Meng wrote:
> >
> > This adds DM drivers to support RISC-V CPU and timer.
> >
> > The U-Boot RISC-V SBI support is still working in progress.
> > Some patches in this series like adding CSR numbers,
On Tue, Nov 13, 2018 at 1:47 PM Bin Meng wrote:
>
> This adds DM drivers to support RISC-V CPU and timer.
>
> The U-Boot RISC-V SBI support is still working in progress.
> Some patches in this series like adding CSR numbers, exception
> numbers, are prerequisites for the SBI implementation, but it
This adds DM drivers to support RISC-V CPU and timer.
The U-Boot RISC-V SBI support is still working in progress.
Some patches in this series like adding CSR numbers, exception
numbers, are prerequisites for the SBI implementation, but it
does no harm to include them as part of this series.
This
5 matches
Mail list logo