Re: [U-Boot] [PATCH 0/6] Add support for loading FPGA bitstream

2019-01-03 Thread Marek Vasut
On 1/3/19 6:33 AM, Chee, Tien Fong wrote: > On Tue, 2019-01-01 at 21:36 +0100, Marek Vasut wrote: >> On 1/1/19 3:52 AM, Chee, Tien Fong wrote: >>> >>> On Sun, 2018-12-30 at 16:44 +0100, Marek Vasut wrote: On 12/30/18 9:13 AM, tien.fong.c...@intel.com wrote: > > > From: Tien Fo

Re: [U-Boot] [PATCH 0/6] Add support for loading FPGA bitstream

2019-01-02 Thread Chee, Tien Fong
On Tue, 2019-01-01 at 21:36 +0100, Marek Vasut wrote: > On 1/1/19 3:52 AM, Chee, Tien Fong wrote: > > > > On Sun, 2018-12-30 at 16:44 +0100, Marek Vasut wrote: > > > > > > On 12/30/18 9:13 AM, tien.fong.c...@intel.com wrote: > > > > > > > > > > > > From: Tien Fong Chee > > > > > > > > These s

Re: [U-Boot] [PATCH 0/6] Add support for loading FPGA bitstream

2019-01-01 Thread Marek Vasut
On 1/1/19 3:52 AM, Chee, Tien Fong wrote: > On Sun, 2018-12-30 at 16:44 +0100, Marek Vasut wrote: >> On 12/30/18 9:13 AM, tien.fong.c...@intel.com wrote: >>> >>> From: Tien Fong Chee >>> >>> These series of patches enable peripheral bitstream being >>> programmed into FPGA >>> to get the DDR up ru

Re: [U-Boot] [PATCH 0/6] Add support for loading FPGA bitstream

2018-12-31 Thread Chee, Tien Fong
On Sun, 2018-12-30 at 16:44 +0100, Marek Vasut wrote: > On 12/30/18 9:13 AM, tien.fong.c...@intel.com wrote: > > > > From: Tien Fong Chee > > > > These series of patches enable peripheral bitstream being > > programmed into FPGA > > to get the DDR up running. This's also called early IO release,

Re: [U-Boot] [PATCH 0/6] Add support for loading FPGA bitstream

2018-12-30 Thread Marek Vasut
On 12/30/18 9:13 AM, tien.fong.c...@intel.com wrote: > From: Tien Fong Chee > > These series of patches enable peripheral bitstream being programmed into FPGA > to get the DDR up running. This's also called early IO release, because the > peripheral bitstream is only initializing FPGA IOs, PLL, I

[U-Boot] [PATCH 0/6] Add support for loading FPGA bitstream

2018-12-30 Thread tien . fong . chee
From: Tien Fong Chee These series of patches enable peripheral bitstream being programmed into FPGA to get the DDR up running. This's also called early IO release, because the peripheral bitstream is only initializing FPGA IOs, PLL, IO48 and DDR. Once DDR is up running, core bitstream from MMC w