On 03/04/2013 18:54, Dirk Behme wrote:
> Am 03.04.2013 11:12, schrieb Stefano Babic:
>> On 21/03/2013 09:03, Dirk Behme wrote:
>>> Reviewing the ECSPI reset handling shows two issues:
>>>
>>
>> Hi Dirk,
>>
>>
>> agree completely, only a very minor question..
>>
>>
>>> +
>>> +reg_ctrl = reg_read
Am 03.04.2013 11:12, schrieb Stefano Babic:
On 21/03/2013 09:03, Dirk Behme wrote:
Reviewing the ECSPI reset handling shows two issues:
Hi Dirk,
agree completely, only a very minor question..
+
+ reg_ctrl = reg_read(®s->ctrl);
As you says, it makes no sense to read back the value
On 21/03/2013 09:03, Dirk Behme wrote:
> Reviewing the ECSPI reset handling shows two issues:
>
Hi Dirk,
agree completely, only a very minor question..
> +
> + reg_ctrl = reg_read(®s->ctrl);
As you says, it makes no sense to read back the value of the register,
also because reg_ctrl is o
Reviewing the ECSPI reset handling shows two issues:
1. For the enable/reset bit (MXC_CSPICTRL_EN) in the control reg
(ECSPIx_CONGREG) the i.MX6 technical reference manual states:
-- cut --
ECSPIx_CONREG[0]: EN: Writing zero to this bit disables the block
and resets the internal logic
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