On Fri, Jun 29, 2018 at 2:02 PM, Marek Vasut wrote:
> On 06/28/2018 04:29 PM, Jagan Teki wrote:
>> On Mon, Jun 18, 2018 at 1:18 PM, Jagan Teki wrote:
>>> On Tue, May 29, 2018 at 2:30 PM, Marek Vasut wrote:
On 05/29/2018 06:52 AM, Jagan Teki wrote:
> + Siva
>
> On Fri, May 25, 20
On 06/28/2018 04:29 PM, Jagan Teki wrote:
> On Mon, Jun 18, 2018 at 1:18 PM, Jagan Teki wrote:
>> On Tue, May 29, 2018 at 2:30 PM, Marek Vasut wrote:
>>> On 05/29/2018 06:52 AM, Jagan Teki wrote:
+ Siva
On Fri, May 25, 2018 at 1:28 AM, Marek Vasut wrote:
> The N25Q256(A) datas
On Mon, Jun 18, 2018 at 1:18 PM, Jagan Teki wrote:
> On Tue, May 29, 2018 at 2:30 PM, Marek Vasut wrote:
>> On 05/29/2018 06:52 AM, Jagan Teki wrote:
>>> + Siva
>>>
>>> On Fri, May 25, 2018 at 1:28 AM, Marek Vasut wrote:
The N25Q256(A) datasheet clearly states that this device does have
>>>
On Tue, May 29, 2018 at 2:30 PM, Marek Vasut wrote:
> On 05/29/2018 06:52 AM, Jagan Teki wrote:
>> + Siva
>>
>> On Fri, May 25, 2018 at 1:28 AM, Marek Vasut wrote:
>>> The N25Q256(A) datasheet clearly states that this device does have
>>> a Flag Status Register and does update FSR PEC bit 7 durin
On 06/06/2018 09:04 PM, Jagan Teki wrote:
> On Thu, Jun 7, 2018 at 12:15 AM, Marek Vasut wrote:
>> On 05/24/2018 09:58 PM, Marek Vasut wrote:
>>> The N25Q256(A) datasheet clearly states that this device does have
>>> a Flag Status Register and does update FSR PEC bit 7 during Program
>>> and Erase
On Thu, Jun 7, 2018 at 12:15 AM, Marek Vasut wrote:
> On 05/24/2018 09:58 PM, Marek Vasut wrote:
>> The N25Q256(A) datasheet clearly states that this device does have
>> a Flag Status Register and does update FSR PEC bit 7 during Program
>> and Erase cycles to indicate the cycle is in progress. En
On 05/24/2018 09:58 PM, Marek Vasut wrote:
> The N25Q256(A) datasheet clearly states that this device does have
> a Flag Status Register and does update FSR PEC bit 7 during Program
> and Erase cycles to indicate the cycle is in progress. Enable the
> FSR PEC bit polling on this device to prevent d
On 05/29/2018 06:52 AM, Jagan Teki wrote:
> + Siva
>
> On Fri, May 25, 2018 at 1:28 AM, Marek Vasut wrote:
>> The N25Q256(A) datasheet clearly states that this device does have
>> a Flag Status Register and does update FSR PEC bit 7 during Program
>> and Erase cycles to indicate the cycle is in p
Hi,
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Tuesday, May 29, 2018 10:22 AM
> To: Marek Vasut ; Siva Durga Prasad Paladugu
>
> Cc: U-Boot Mailing List ; Tom Rini
>
> Subject: Re: [U-Boot] [PATCH] sf: Enable FSR polling o
+ Siva
On Fri, May 25, 2018 at 1:28 AM, Marek Vasut wrote:
> The N25Q256(A) datasheet clearly states that this device does have
> a Flag Status Register and does update FSR PEC bit 7 during Program
> and Erase cycles to indicate the cycle is in progress. Enable the
> FSR PEC bit polling on this d
The N25Q256(A) datasheet clearly states that this device does have
a Flag Status Register and does update FSR PEC bit 7 during Program
and Erase cycles to indicate the cycle is in progress. Enable the
FSR PEC bit polling on this device to prevent data corruption.
Signed-off-by: Marek Vasut
Cc: Ja
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