Re: [U-Boot] [PATCH] ppc/85xx: Fix bug in setup_mp code

2010-01-21 Thread Peter Tyser
Hi Ed, On Thu, 2010-01-21 at 15:06 -0700, Swarthout Edward L-SWARTHOU wrote: > From: Kumar Gala > > > Its possible that we try and copy the boot page code out of flash into > > > a DDR location that doesn't have a TLB cover it. For example, if we > > have 3G of DDR we typically only map the fi

Re: [U-Boot] [PATCH] ppc/85xx: Fix bug in setup_mp code

2010-01-21 Thread Swarthout Edward L-SWARTHOU
From: Kumar Gala > Its possible that we try and copy the boot page code out of flash into > a DDR location that doesn't have a TLB cover it. For example, if we > have 3G of DDR we typically only map the first 2G. In the cases of > 4G+ this wasn't an issue since the reset page TLB mapping cove

Re: [U-Boot] [PATCH] ppc/85xx: Fix bug in setup_mp code

2009-09-05 Thread Kumar Gala
On Sep 3, 2009, at 8:58 AM, Kumar Gala wrote: > Its possible that we try and copy the boot page code out of flash > into a > DDR location that doesn't have a TLB cover it. For example, if we > have > 3G of DDR we typically only map the first 2G. In the cases of 4G+ > this > wasn't an issu

Re: [U-Boot] [PATCH] ppc/85xx: Fix bug in setup_mp code

2009-09-03 Thread Kumar Gala
On Sep 3, 2009, at 9:41 AM, Peter Tyser wrote: > On Thu, 2009-09-03 at 08:58 -0500, Kumar Gala wrote: >> Its possible that we try and copy the boot page code out of flash >> into a >> DDR location that doesn't have a TLB cover it. For example, if we >> have >> 3G of DDR we typically only map

Re: [U-Boot] [PATCH] ppc/85xx: Fix bug in setup_mp code

2009-09-03 Thread Peter Tyser
On Thu, 2009-09-03 at 08:58 -0500, Kumar Gala wrote: > Its possible that we try and copy the boot page code out of flash into a > DDR location that doesn't have a TLB cover it. For example, if we have > 3G of DDR we typically only map the first 2G. In the cases of 4G+ this > wasn't an issue since

[U-Boot] [PATCH] ppc/85xx: Fix bug in setup_mp code

2009-09-03 Thread Kumar Gala
Its possible that we try and copy the boot page code out of flash into a DDR location that doesn't have a TLB cover it. For example, if we have 3G of DDR we typically only map the first 2G. In the cases of 4G+ this wasn't an issue since the reset page TLB mapping covered the last page of memory w