Re: [U-Boot] [PATCH] powerpc/p2041: configure the CPLD lane_mux according to RCW

2012-08-08 Thread Andy Fleming
On Fri, Jun 29, 2012 at 4:37 AM, Shaohui Xie wrote: > Lane muxing on p2041 is controlled by a reg in CPLD, offset of this reg > is 0xc, CPLD supports SATA by default, we should re-configure the lane > muxing according to RCW, which indicates what SerDes protocol it is running. > > Default lane mux

[U-Boot] [PATCH] powerpc/p2041: configure the CPLD lane_mux according to RCW

2012-06-29 Thread Shaohui Xie
Lane muxing on p2041 is controlled by a reg in CPLD, offset of this reg is 0xc, CPLD supports SATA by default, we should re-configure the lane muxing according to RCW, which indicates what SerDes protocol it is running. Default lane muxing map is as below: Lane G on bank1 routes to SGMII, controll