On Mar 15, 2011, at 1:25 AM, Kumar Gala wrote:
> There is a small ordering issue in the master core in that we need to
> make sure the disabling of the timebase in the SoC is visible before we
> set the value to 0. We can simply just read back the value to
> synchronizatize the write, before we
There is a small ordering issue in the master core in that we need to
make sure the disabling of the timebase in the SoC is visible before we
set the value to 0. We can simply just read back the value to
synchronizatize the write, before we set TB to 0.
Reported-by: Dan Hettena
Tested-by: Dan Het
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