Hi Stefano,
On Fri, May 15, 2015 at 10:35 AM, Stefano Babic wrote:
> It looks like from the discussion and the following threads that a
> general solution cannot be easy found. I agree with you to apply it at
> least for i.MX6, and let's see if in the future we can factorize it for
> other SOCs.
Hi Fabio,
On 11/03/2015 21:12, Fabio Estevam wrote:
> From: Fabio Estevam
>
> Having bit 22 cleared in the PL310 Auxiliary Control register (shared
> attribute override enable) has the side effect of transforming Normal
> Shared Non-cacheable reads into Cacheable no-allocate reads.
>
> Coherent
On Thu, Mar 12, 2015 at 10:15 AM, Fabio Estevam wrote:
> On Thu, Mar 12, 2015 at 11:43 AM, Nishanth Menon wrote:
>
>> I dont think this works for OMAP4 (which also uses A9, PL310) - we use
>> an smc #0 with service 0x109 (I have to reconfirm) to set l2 aux_ctrl.
>>
>> https://git.kernel.org/cgit/
On Thu, Mar 12, 2015 at 11:43 AM, Nishanth Menon wrote:
> I dont think this works for OMAP4 (which also uses A9, PL310) - we use
> an smc #0 with service 0x109 (I have to reconfirm) to set l2 aux_ctrl.
>
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/mach-omap2/om
On 03/12/2015 09:25 AM, Fabio Estevam wrote:
> Tom/Nishanth,
>
> On Thu, Mar 12, 2015 at 10:57 AM, Fabio Estevam wrote:
>> On Thu, Mar 12, 2015 at 10:41 AM, Tom Rini wrote:
>>
>>> We should put this somewhere a bit more common that other A9 cores can
>>> also call into like OMAP4, SoCFPGA and ma
Tom/Nishanth,
On Thu, Mar 12, 2015 at 10:57 AM, Fabio Estevam wrote:
> On Thu, Mar 12, 2015 at 10:41 AM, Tom Rini wrote:
>
>> We should put this somewhere a bit more common that other A9 cores can
>> also call into like OMAP4, SoCFPGA and maybe zynq later (based on a
>> quick git grep pl310).
>
On 03/11/2015 03:12 PM, Fabio Estevam wrote:
> From: Fabio Estevam
>
> Having bit 22 cleared in the PL310 Auxiliary Control register (shared
> attribute override enable) has the side effect of transforming Normal
> Shared Non-cacheable reads into Cacheable no-allocate reads.
>
> Coherent DMA buf
On Thu, Mar 12, 2015 at 10:41 AM, Tom Rini wrote:
> We should put this somewhere a bit more common that other A9 cores can
> also call into like OMAP4, SoCFPGA and maybe zynq later (based on a
> quick git grep pl310).
I thought about it as well, but I didn't find a suitable common place
for putt
On Wed, Mar 11, 2015 at 05:12:12PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam
>
> Having bit 22 cleared in the PL310 Auxiliary Control register (shared
> attribute override enable) has the side effect of transforming Normal
> Shared Non-cacheable reads into Cacheable no-allocate reads.
>
On Thu, Mar 12, 2015 at 01:04:31AM +, Russell King - ARM Linux wrote:
> On Wed, Mar 11, 2015 at 05:12:12PM -0300, Fabio Estevam wrote:
> > From: Fabio Estevam
> >
> > Having bit 22 cleared in the PL310 Auxiliary Control register (shared
> > attribute override enable) has the side effect of tr
On Wed, Mar 11, 2015 at 08:12:12PM +, Fabio Estevam wrote:
> From: Fabio Estevam
>
> Having bit 22 cleared in the PL310 Auxiliary Control register (shared
> attribute override enable) has the side effect of transforming Normal
> Shared Non-cacheable reads into Cacheable no-allocate reads.
>
On Wed, Mar 11, 2015 at 10:04 PM, Russell King - ARM Linux
wrote:
> No, this is wrong. They do not. CMA remaps pages to be non-cacheable
> rather than the old technique where the above statement was true.
>
> There's some corner cases which make that less effective than it once
> was, and as I'
On Wed, Mar 11, 2015 at 05:12:12PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam
>
> Having bit 22 cleared in the PL310 Auxiliary Control register (shared
> attribute override enable) has the side effect of transforming Normal
> Shared Non-cacheable reads into Cacheable no-allocate reads.
>
From: Fabio Estevam
Having bit 22 cleared in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel
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