Re: [U-Boot] [PATCH] imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask

2016-03-25 Thread Stefano Babic
On 25/03/2016 10:14, Peng Fan wrote: > Hi Stefano, > > On Wed, Mar 09, 2016 at 05:37:28PM +0800, Peng Fan wrote: >> Hi Stefano, >> >> On Wed, Mar 09, 2016 at 10:47:38AM +0100, Stefano Babic wrote: >>> Hi Peng, Ye, >>> >>> On 09/03/2016 09:13, Peng Fan wrote: From: Ye Li Since the M

Re: [U-Boot] [PATCH] imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask

2016-03-25 Thread Peng Fan
Hi Stefano, On Wed, Mar 09, 2016 at 05:37:28PM +0800, Peng Fan wrote: >Hi Stefano, > >On Wed, Mar 09, 2016 at 10:47:38AM +0100, Stefano Babic wrote: >>Hi Peng, Ye, >> >>On 09/03/2016 09:13, Peng Fan wrote: >>> From: Ye Li >>> >>> Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR regist

Re: [U-Boot] [PATCH] imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask

2016-03-09 Thread Peng Fan
Hi Stefano, On Wed, Mar 09, 2016 at 10:47:38AM +0100, Stefano Babic wrote: >Hi Peng, Ye, > >On 09/03/2016 09:13, Peng Fan wrote: >> From: Ye Li >> >> Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register >> the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. >>

Re: [U-Boot] [PATCH] imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask

2016-03-09 Thread Stefano Babic
Hi Peng, Ye, On 09/03/2016 09:13, Peng Fan wrote: > From: Ye Li > > Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register > the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. > When clear this bit, the periph_clk_sel cannot be set and that > CDHIPR[periph_clk_s

[U-Boot] [PATCH] imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask

2016-03-09 Thread Peng Fan
From: Ye Li Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit, the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake never clears. Signed-off-by: Ye Li Signed-