Re: [U-Boot] [PATCH] fsl_esdhc: Deal with watermark level register related changes

2011-04-10 Thread Kumar Gala
On Apr 10, 2011, at 10:30 AM, Stefano Babic wrote: > On 03/07/2011 05:14 AM, Kumar Gala wrote: >> From: Priyanka Jain >> >> P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark >> level register description has been changed: >> >> 9-15 bits represent WR_WML[0:6], Max val

Re: [U-Boot] [PATCH] fsl_esdhc: Deal with watermark level register related changes

2011-04-10 Thread Stefano Babic
On 03/07/2011 05:14 AM, Kumar Gala wrote: > From: Priyanka Jain > > P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark > level register description has been changed: > > 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 > 25-31 bits represent RD_WML[0:

Re: [U-Boot] [PATCH] fsl_esdhc: Deal with watermark level register related changes

2011-04-04 Thread Kumar Gala
On Mar 6, 2011, at 10:14 PM, Kumar Gala wrote: > From: Priyanka Jain > > P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark > level register description has been changed: > > 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 > 25-31 bits represent RD

[U-Boot] [PATCH] fsl_esdhc: Deal with watermark level register related changes

2011-03-06 Thread Kumar Gala
From: Priyanka Jain P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark level register description has been changed: 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00 Signed-off-by: