> Read-to-read/Write-to-write turnaround for same chip select
> of DDR3 memory, BL/2+2 cycles is enough for these turnarounds.
> Cutting down the turnaround from BL/2+4 to BL/2+2 will improve
> the memory performance.
Please ignore this patch, I will provide one better solution to address
this per
Read-to-read/Write-to-write turnaround for same chip select
of DDR3 memory, BL/2+2 cycles is enough for these turnarounds.
Cutting down the turnaround from BL/2+4 to BL/2+2 will improve
the memory performance.
Signed-off-by: Dave Liu
---
cpu/mpc8xxx/ddr/ctrl_regs.c |6 +++---
1 files changed
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