> -Original Message-
> From: york sun
> Sent: Saturday, January 30, 2016 4:40 AM
> To: Mingkai Hu; u-boot@lists.denx.de
> Subject: Re: [PATCH] armv8/ls1043a: Implement workaround for erratum
> A009660
>
> On 01/25/2016 10:12 PM, Mingkai Hu wrote:
> >
> >
> >> -Original Message-
>
On 01/25/2016 10:12 PM, Mingkai Hu wrote:
>
>
>> -Original Message-
>> From: york sun
>> Sent: Saturday, January 23, 2016 1:44 AM
>> To: Mingkai Hu; Mingkai Hu; u-boot@lists.denx.de
>> Subject: Re: [PATCH] armv8/ls1043a: Implement workaround for erratum
>> A009660
>>
>> On 01/21/2016 11:5
> -Original Message-
> From: york sun
> Sent: Saturday, January 23, 2016 1:44 AM
> To: Mingkai Hu; Mingkai Hu; u-boot@lists.denx.de
> Subject: Re: [PATCH] armv8/ls1043a: Implement workaround for erratum
> A009660
>
> On 01/21/2016 11:50 PM, Mingkai Hu wrote:
> >
> >
> >> -Original Me
On 01/21/2016 11:50 PM, Mingkai Hu wrote:
>
>
>> -Original Message-
>> From: Mingkai Hu
>> Sent: Thursday, January 21, 2016 11:18 AM
>> To: york sun; Mingkai Hu; u-boot@lists.denx.de
>> Subject: RE: [PATCH] armv8/ls1043a: Implement workaround for erratum
>> A009660
>>
>>
>>
>>> -Origi
> -Original Message-
> From: Mingkai Hu
> Sent: Thursday, January 21, 2016 11:18 AM
> To: york sun; Mingkai Hu; u-boot@lists.denx.de
> Subject: RE: [PATCH] armv8/ls1043a: Implement workaround for erratum
> A009660
>
>
>
> > -Original Message-
> > From: york sun
> > Sent: Thursd
> -Original Message-
> From: york sun
> Sent: Thursday, January 21, 2016 12:21 AM
> To: Mingkai Hu; u-boot@lists.denx.de
> Cc: Mingkai Hu
> Subject: Re: [PATCH] armv8/ls1043a: Implement workaround for erratum
> A009660
>
> On 01/19/2016 10:44 PM, Mingkai Hu wrote:
> > From: Mingkai Hu
>
On 01/19/2016 10:44 PM, Mingkai Hu wrote:
> From: Mingkai Hu
>
> Memory controller performance is not optimal with default internal
> target queue register value, write required value for optimal DDR
> performance.
>
> Signed-off-by: Mingkai Hu
> ---
> arch/arm/cpu/armv8/fsl-layerscape/soc.c
From: Mingkai Hu
Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.
Signed-off-by: Mingkai Hu
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 13 +
arch/arm/include/asm/arch-fsl-l
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