Re: [U-Boot] [PATCH] arm: socfpga: set the mpuclk divider in the Altera group register

2017-02-09 Thread Marek Vasut
On 02/09/2017 04:29 AM, Dinh Nguyen wrote: > On Wed, Feb 8, 2017 at 5:23 PM, Marek Vasut wrote: >> On 02/08/2017 11:51 PM, Dinh Nguyen wrote: >>> >>> >>> On 02/08/2017 03:04 PM, Marek Vasut wrote: On 02/08/2017 06:59 PM, Dinh Nguyen wrote: > > > On 02/07/2017 07:32 PM, Marek Vasut

Re: [U-Boot] [PATCH] arm: socfpga: set the mpuclk divider in the Altera group register

2017-02-08 Thread Dinh Nguyen
On Wed, Feb 8, 2017 at 5:23 PM, Marek Vasut wrote: > On 02/08/2017 11:51 PM, Dinh Nguyen wrote: >> >> >> On 02/08/2017 03:04 PM, Marek Vasut wrote: >>> On 02/08/2017 06:59 PM, Dinh Nguyen wrote: On 02/07/2017 07:32 PM, Marek Vasut wrote: > On 02/08/2017 02:21 AM, Marek Vasut wro

Re: [U-Boot] [PATCH] arm: socfpga: set the mpuclk divider in the Altera group register

2017-02-08 Thread Marek Vasut
On 02/08/2017 11:51 PM, Dinh Nguyen wrote: > > > On 02/08/2017 03:04 PM, Marek Vasut wrote: >> On 02/08/2017 06:59 PM, Dinh Nguyen wrote: >>> >>> >>> On 02/07/2017 07:32 PM, Marek Vasut wrote: On 02/08/2017 02:21 AM, Marek Vasut wrote: > On 01/31/2017 07:33 PM, Dinh Nguyen wrote: >>

Re: [U-Boot] [PATCH] arm: socfpga: set the mpuclk divider in the Altera group register

2017-02-08 Thread Dinh Nguyen
On 02/08/2017 03:04 PM, Marek Vasut wrote: > On 02/08/2017 06:59 PM, Dinh Nguyen wrote: >> >> >> On 02/07/2017 07:32 PM, Marek Vasut wrote: >>> On 02/08/2017 02:21 AM, Marek Vasut wrote: On 01/31/2017 07:33 PM, Dinh Nguyen wrote: > The mpuclk register in the Altera group of the clock man

Re: [U-Boot] [PATCH] arm: socfpga: set the mpuclk divider in the Altera group register

2017-02-08 Thread Marek Vasut
On 02/08/2017 06:59 PM, Dinh Nguyen wrote: > > > On 02/07/2017 07:32 PM, Marek Vasut wrote: >> On 02/08/2017 02:21 AM, Marek Vasut wrote: >>> On 01/31/2017 07:33 PM, Dinh Nguyen wrote: The mpuclk register in the Altera group of the clock manager divides the mpu_clk that is generated fro

Re: [U-Boot] [PATCH] arm: socfpga: set the mpuclk divider in the Altera group register

2017-02-08 Thread Dinh Nguyen
On 02/07/2017 07:32 PM, Marek Vasut wrote: > On 02/08/2017 02:21 AM, Marek Vasut wrote: >> On 01/31/2017 07:33 PM, Dinh Nguyen wrote: >>> The mpuclk register in the Altera group of the clock manager >>> divides the mpu_clk that is generated from the C0 output of the main >>> pll. >>> >>> Without

Re: [U-Boot] [PATCH] arm: socfpga: set the mpuclk divider in the Altera group register

2017-02-07 Thread Marek Vasut
On 02/08/2017 02:21 AM, Marek Vasut wrote: > On 01/31/2017 07:33 PM, Dinh Nguyen wrote: >> The mpuclk register in the Altera group of the clock manager >> divides the mpu_clk that is generated from the C0 output of the main >> pll. >> >> Without this patch, the default value of the register is 1, s

Re: [U-Boot] [PATCH] arm: socfpga: set the mpuclk divider in the Altera group register

2017-02-07 Thread Marek Vasut
On 01/31/2017 07:33 PM, Dinh Nguyen wrote: > The mpuclk register in the Altera group of the clock manager > divides the mpu_clk that is generated from the C0 output of the main > pll. > > Without this patch, the default value of the register is 1, so the mpuclk > will always get divided by 2 if th

Re: [U-Boot] [PATCH] arm: socfpga: set the mpuclk divider in the Altera group register

2017-02-04 Thread Marek Vasut
On 01/31/2017 07:33 PM, Dinh Nguyen wrote: > The mpuclk register in the Altera group of the clock manager > divides the mpu_clk that is generated from the C0 output of the main > pll. > > Without this patch, the default value of the register is 1, so the mpuclk > will always get divided by 2 if th

[U-Boot] [PATCH] arm: socfpga: set the mpuclk divider in the Altera group register

2017-01-31 Thread Dinh Nguyen
The mpuclk register in the Altera group of the clock manager divides the mpu_clk that is generated from the C0 output of the main pll. Without this patch, the default value of the register is 1, so the mpuclk will always get divided by 2 if the correct value is not set. For example, on the Arria5