On Thu, Feb 14, 2019 at 4:37 PM Dinh Nguyen wrote:
>
> Hi Marek,
>
> On 2/9/19 4:01 AM, Marek Vasut wrote:
> > On 2/7/19 10:23 PM, Simon Goldschmidt wrote:
> >> To clean up reset handling for socfpga gen5, let's move the code snippet
> >> taking the DDR controller out of reset from SPL to the DDR
Hi Marek,
On 2/9/19 4:01 AM, Marek Vasut wrote:
> On 2/7/19 10:23 PM, Simon Goldschmidt wrote:
>> To clean up reset handling for socfpga gen5, let's move the code snippet
>> taking the DDR controller out of reset from SPL to the DDR driver.
>>
>> While at it, port the ddr driver to UCLASS_RAM and
Am 09.02.2019 um 11:38 schrieb Simon Goldschmidt:
On Sat, Feb 9, 2019 at 11:25 AM Marek Vasut wrote:
On 2/7/19 10:23 PM, Simon Goldschmidt wrote:
To clean up reset handling for socfpga gen5, let's move the code snippet
taking the DDR controller out of reset from SPL to the DDR driver.
While
Am 11.02.2019 um 19:38 schrieb Dalon L Westergreen:
On Sat, 2019-02-09 at 11:02 +0100, Marek Vasut wrote:
On 2/8/19 11:51 PM, Dalon L Westergreen wrote:
On Fri, 2019-02-08 at 21:36 +0100, Simon Goldschmidt wrote:
Am Fr., 8. Feb. 2019, 21:28 hat Dalon L Westergreen <
dalon.westergr...@linux.in
On Sat, 2019-02-09 at 11:02 +0100, Marek Vasut wrote:
> On 2/8/19 11:51 PM, Dalon L Westergreen wrote:
> > On Fri, 2019-02-08 at 21:36 +0100, Simon Goldschmidt wrote:
> > >
> > > Am Fr., 8. Feb. 2019, 21:28 hat Dalon L Westergreen <
> > > dalon.westergr...@linux.intel.com> geschrieben:
> > > > On
On Sat, Feb 9, 2019 at 11:25 AM Marek Vasut wrote:
>
> On 2/7/19 10:23 PM, Simon Goldschmidt wrote:
> > To clean up reset handling for socfpga gen5, let's move the code snippet
> > taking the DDR controller out of reset from SPL to the DDR driver.
> >
> > While at it, port the ddr driver to UCLASS
On 2/8/19 11:51 PM, Dalon L Westergreen wrote:
> On Fri, 2019-02-08 at 21:36 +0100, Simon Goldschmidt wrote:
>>
>>
>> Am Fr., 8. Feb. 2019, 21:28 hat Dalon L Westergreen <
>> dalon.westergr...@linux.intel.com> geschrieben:
>>> On Thu, 2019-02-07 at 22:23 +0100, Simon Goldschmidt wrote:
To clea
On Fri, 2019-02-08 at 21:36 +0100, Simon Goldschmidt wrote:
>
>
> Am Fr., 8. Feb. 2019, 21:28 hat Dalon L Westergreen <
> dalon.westergr...@linux.intel.com> geschrieben:
> > On Thu, 2019-02-07 at 22:23 +0100, Simon Goldschmidt wrote:
> > > To clean up reset handling for socfpga gen5, let's move t
Am Fr., 8. Feb. 2019, 21:28 hat Dalon L Westergreen <
dalon.westergr...@linux.intel.com> geschrieben:
> On Thu, 2019-02-07 at 22:23 +0100, Simon Goldschmidt wrote:
> > To clean up reset handling for socfpga gen5, let's move the code snippet
> > taking the DDR controller out of reset from SPL to th
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