On 02/14/2017 09:23 AM, Dalon Westergreen wrote:
> When CSEL=0x0 the socfpga bootrom does not touch the clock
> configuration for the device. This can lead to a boot failure
> on warm resets. To address this, the bootrom is configured to
> run a bit of code in the last 4KB of onchip ram on a wa
When CSEL=0x0 the socfpga bootrom does not touch the clock
configuration for the device. This can lead to a boot failure
on warm resets. To address this, the bootrom is configured to
run a bit of code in the last 4KB of onchip ram on a warm reset.
This code puts the PLLs in bypass, disables the b
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