On Tue, 2015-02-10 at 13:38 +0300, Alexey Brodkin wrote:
> ARC HS and ARC EM are new cores based on ARCv2 ISA which is binary
> incompatible with ISAv1 (AKA ARCompact).
>
> Significant difference between ISAv2 and v1 is implementation of
> interrupt vector table.
>
> In v1 it is implemented in th
ARC HS and ARC EM are new cores based on ARCv2 ISA which is binary
incompatible with ISAv1 (AKA ARCompact).
Significant difference between ISAv2 and v1 is implementation of
interrupt vector table.
In v1 it is implemented in the same way as on many other architectures -
as a special location where
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