Re: [U-Boot] [PATCH] ARM: socfpga: Clear PL310 early in SPL

On 2/19/19 9:56 PM, Simon Goldschmidt wrote: > Am 19.02.2019 um 21:07 schrieb Marek Vasut: >> On 2/19/19 8:29 PM, Simon Goldschmidt wrote: >>> Am 19.02.2019 um 17:39 schrieb Marek Vasut: On 2/19/19 5:31 PM, Simon Goldschmidt wrote: > Am 19.02.2019 um 17:00 schrieb Marek Vasut: >> On 2/

Re: [U-Boot] [PATCH] ARM: socfpga: Clear PL310 early in SPL

Am 19.02.2019 um 21:07 schrieb Marek Vasut: On 2/19/19 8:29 PM, Simon Goldschmidt wrote: Am 19.02.2019 um 17:39 schrieb Marek Vasut: On 2/19/19 5:31 PM, Simon Goldschmidt wrote: Am 19.02.2019 um 17:00 schrieb Marek Vasut: On 2/19/19 4:55 PM, Simon Goldschmidt wrote: Am 19.02.2019 um 15:00 sc

Re: [U-Boot] [PATCH] ARM: socfpga: Clear PL310 early in SPL

On 2/19/19 8:29 PM, Simon Goldschmidt wrote: > Am 19.02.2019 um 17:39 schrieb Marek Vasut: >> On 2/19/19 5:31 PM, Simon Goldschmidt wrote: >>> Am 19.02.2019 um 17:00 schrieb Marek Vasut: On 2/19/19 4:55 PM, Simon Goldschmidt wrote: > Am 19.02.2019 um 15:00 schrieb Marek Vasut: >> On 2/

Re: [U-Boot] [PATCH] ARM: socfpga: Clear PL310 early in SPL

Am 19.02.2019 um 17:39 schrieb Marek Vasut: On 2/19/19 5:31 PM, Simon Goldschmidt wrote: Am 19.02.2019 um 17:00 schrieb Marek Vasut: On 2/19/19 4:55 PM, Simon Goldschmidt wrote: Am 19.02.2019 um 15:00 schrieb Marek Vasut: On 2/19/19 2:58 PM, Simon Goldschmidt wrote: Am Di., 19. Feb. 2019,

Re: [U-Boot] [PATCH] ARM: socfpga: Clear PL310 early in SPL

On 2/19/19 5:31 PM, Simon Goldschmidt wrote: > Am 19.02.2019 um 17:00 schrieb Marek Vasut: >> On 2/19/19 4:55 PM, Simon Goldschmidt wrote: >>> Am 19.02.2019 um 15:00 schrieb Marek Vasut: On 2/19/19 2:58 PM, Simon Goldschmidt wrote: > > > Am Di., 19. Feb. 2019, 14:45 hat Marek Vasut

Re: [U-Boot] [PATCH] ARM: socfpga: Clear PL310 early in SPL

Am 19.02.2019 um 17:00 schrieb Marek Vasut: On 2/19/19 4:55 PM, Simon Goldschmidt wrote: Am 19.02.2019 um 15:00 schrieb Marek Vasut: On 2/19/19 2:58 PM, Simon Goldschmidt wrote: Am Di., 19. Feb. 2019, 14:45 hat Marek Vasut mailto:ma...@denx.de>> geschrieben: On 2/19/19 2:28 PM, Simon

Re: [U-Boot] [PATCH] ARM: socfpga: Clear PL310 early in SPL

On 2/19/19 4:55 PM, Simon Goldschmidt wrote: > Am 19.02.2019 um 15:00 schrieb Marek Vasut: >> On 2/19/19 2:58 PM, Simon Goldschmidt wrote: >>> >>> >>> Am Di., 19. Feb. 2019, 14:45 hat Marek Vasut >> > geschrieben: >>> >>> On 2/19/19 2:28 PM, Simon Goldschmidt wrote: >>>  

Re: [U-Boot] [PATCH] ARM: socfpga: Clear PL310 early in SPL

Am 19.02.2019 um 15:00 schrieb Marek Vasut: On 2/19/19 2:58 PM, Simon Goldschmidt wrote: Am Di., 19. Feb. 2019, 14:45 hat Marek Vasut mailto:ma...@denx.de>> geschrieben: On 2/19/19 2:28 PM, Simon Goldschmidt wrote: > On Tue, Feb 19, 2019 at 1:53 PM Marek Vasut mailto:ma...@denx.de>>

Re: [U-Boot] [PATCH] ARM: socfpga: Clear PL310 early in SPL

On 2/19/19 2:58 PM, Simon Goldschmidt wrote: > > > Am Di., 19. Feb. 2019, 14:45 hat Marek Vasut > geschrieben: > > On 2/19/19 2:28 PM, Simon Goldschmidt wrote: > > On Tue, Feb 19, 2019 at 1:53 PM Marek Vasut > wrote: > >> > >> On

Re: [U-Boot] [PATCH] ARM: socfpga: Clear PL310 early in SPL

Am Di., 19. Feb. 2019, 14:45 hat Marek Vasut geschrieben: > On 2/19/19 2:28 PM, Simon Goldschmidt wrote: > > On Tue, Feb 19, 2019 at 1:53 PM Marek Vasut wrote: > >> > >> On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux > >> will result in stale data in PL310 L2 cache contro

Re: [U-Boot] [PATCH] ARM: socfpga: Clear PL310 early in SPL

On 2/19/19 2:28 PM, Simon Goldschmidt wrote: > On Tue, Feb 19, 2019 at 1:53 PM Marek Vasut wrote: >> >> On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux >> will result in stale data in PL310 L2 cache controller. Even if the L2 >> cache controller is disabled via the CTRL regi

Re: [U-Boot] [PATCH] ARM: socfpga: Clear PL310 early in SPL

On Tue, Feb 19, 2019 at 1:53 PM Marek Vasut wrote: > > On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux > will result in stale data in PL310 L2 cache controller. Even if the L2 > cache controller is disabled via the CTRL register CTRL_EN bit, those > data can interfere with o

[U-Boot] [PATCH] ARM: socfpga: Clear PL310 early in SPL

On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux will result in stale data in PL310 L2 cache controller. Even if the L2 cache controller is disabled via the CTRL register CTRL_EN bit, those data can interfere with operation of devices using DMA, like e.g. the DWMMC controller.