Re: [U-Boot] [PATCH] ARM: mx6: ddr: Add write leveling correction code

2018-04-15 Thread Stefano Babic
On 30/03/2018 03:04, Marek Vasut wrote: > When the DDR calibration is enabled, a situation may happen that it > will fail on a few select boards out of a whole production lot. In > particular, after the first write leveling stage, the MPWLDECTRLx > registers will contain a value 0x1nn , for nn us

Re: [U-Boot] [PATCH] ARM: mx6: ddr: Add write leveling correction code

2018-04-03 Thread Stefano Babic
On 30/03/2018 03:04, Marek Vasut wrote: > When the DDR calibration is enabled, a situation may happen that it > will fail on a few select boards out of a whole production lot. In > particular, after the first write leveling stage, the MPWLDECTRLx > registers will contain a value 0x1nn , for nn usua

Re: [U-Boot] [PATCH] ARM: mx6: ddr: Add write leveling correction code

2018-04-03 Thread Stefano Babic
On 30/03/2018 18:10, Eric Nelson wrote: > Hi Marek, > > Thanks for this update and the detailed notes. > > On 03/29/2018 06:04 PM, Marek Vasut wrote: >> When the DDR calibration is enabled, a situation may happen that it >> will fail on a few select boards out of a whole production lot. In >> par

Re: [U-Boot] [PATCH] ARM: mx6: ddr: Add write leveling correction code

2018-03-30 Thread Eric Nelson
Hi Marek, Thanks for this update and the detailed notes. On 03/29/2018 06:04 PM, Marek Vasut wrote: When the DDR calibration is enabled, a situation may happen that it will fail on a few select boards out of a whole production lot. In particular, after the first write leveling stage, the MPWLDE

Re: [U-Boot] [PATCH] ARM: mx6: ddr: Add write leveling correction code

2018-03-30 Thread Fabio Estevam
Hi Marek, On Thu, Mar 29, 2018 at 10:04 PM, Marek Vasut wrote: > When the DDR calibration is enabled, a situation may happen that it > will fail on a few select boards out of a whole production lot. In > particular, after the first write leveling stage, the MPWLDECTRLx > registers will contain a

[U-Boot] [PATCH] ARM: mx6: ddr: Add write leveling correction code

2018-03-29 Thread Marek Vasut
When the DDR calibration is enabled, a situation may happen that it will fail on a few select boards out of a whole production lot. In particular, after the first write leveling stage, the MPWLDECTRLx registers will contain a value 0x1nn , for nn usually being 0x7f or slightly lower. What this mea