Re: [U-Boot] [PATCH] 8xxx: ddr3: Adjust timings for tRRD, tWTR, and tRTP

2011-03-14 Thread York Sun
On Thu, 2011-03-10 at 16:54 -0600, Peter Tyser wrote: > From: John Schmoller > > The JEDEC DDR3 specification states that the above parameters should > be set to a minimum of 4 clocks. The SPD defines the values in > nanoseconds, and depending on the clock frequency the value in the > SPD can be

[U-Boot] [PATCH] 8xxx: ddr3: Adjust timings for tRRD, tWTR, and tRTP

2011-03-10 Thread Peter Tyser
From: John Schmoller The JEDEC DDR3 specification states that the above parameters should be set to a minimum of 4 clocks. The SPD defines the values in nanoseconds, and depending on the clock frequency the value in the SPD can be less than 4 clocks. Previously, we were only using the values fr