Re: [RFC PATCH] riscv: cpu: check U-Mode before counteren write

On Wed, Dec 14, 2022 at 08:58:43AM +0300, Nikita Shubin wrote: > From: Nikita Shubin > > The Priv ISA states: > "In systems without U-mode, the mcounteren register should > not exist." > > Check U-Mode is present in MISA before writing to counteren, otherwise > we endup with Illegal Instruction

[RFC PATCH] riscv: cpu: check U-Mode before counteren write

From: Nikita Shubin The Priv ISA states: "In systems without U-mode, the mcounteren register should not exist." Check U-Mode is present in MISA before writing to counteren, otherwise we endup with Illegal Instruction exception on systems without U-Mode. Also make checking MISA default for M-Mod