On Wed, Aug 19, 2020 at 03:17:24PM +0200, Marek Bykowski wrote:
> > I think this will have to wait for you to return from holidays and
> > investigate more. All I know is that the QEMU models are working as
> > expected prior to the patch and fail with it.
> >
> > --
> > Tom
>
> From the esr (Ex
> I think this will have to wait for you to return from holidays and
> investigate more. All I know is that the QEMU models are working as
> expected prior to the patch and fail with it.
>
> --
> Tom
>From the esr (Exception Syndrome Register) = 0x964F:
- EC (Exception Class) -> it is an exce
On Tue, Jul 21, 2020 at 02:33:03AM +0200, Marek wrote:
> I'm on holidays right now, seeing the logs in my mobile I cannot infer much.
>
> What's the memory map after the patch? Intentional? I mean the
> code/instruction region is read-only and executable and else read-write and
> non-executable?
I'm on holidays right now, seeing the logs in my mobile I cannot infer much.
What's the memory map after the patch? Intentional? I mean the
code/instruction region is read-only and executable and else read-write and
non-executable?
May it happen that the tests try to write to instruction, read-on
On Fri, Jun 19, 2020 at 02:53:32PM +0200, marek.bykow...@gmail.com wrote:
> From: Marek Bykowski
>
> If the location the ARM CPU is accessing is executable (translation
> table descriptor Execute-Never attribute bit cleared) then the ARM CPU
> fetches a number of instructions from that location
On Fri, Jun 19, 2020 at 02:53:32PM +0200, Marek Bykowski wrote:
> From: Marek Bykowski
>
> However if we fail programming so and the instruction fetch logic goes
> mispredict to non-instruction memory it may eventually perturb it, eg.
> corrupt the FIFO, or the control registers, load the unified
From: Marek Bykowski
If the location the ARM CPU is accessing is executable (translation
table descriptor Execute-Never attribute bit cleared) then the ARM CPU
fetches a number of instructions from that location all at the same time.
For example, Cortex-A57 can source up to 128 bits per fetch dep
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