Re: [PATCH v3 7/7] drivers: ddr: altera: Fix Cylcone5 SPL boot loop issue

Anuar Subject: [PATCH v3 7/7] drivers: ddr: altera: Fix Cylcone5 SPL boot loop issue Hardware watchdog configuration is handled correctly to resolve the SPL boot loop issue on Cyclone5. When hardware watchdog is enabled, it is reconfigured to make the defined timeout valid, else, making sure it is

RE: [PATCH v3 7/7] drivers: ddr: altera: Fix Cylcone5 SPL boot loop issue

ubject: [PATCH v3 7/7] drivers: ddr: altera: Fix Cylcone5 SPL boot loop issue > > Hardware watchdog configuration is handled correctly to resolve the SPL > boot loop issue on Cyclone5. When hardware watchdog is enabled, it is > reconfigured to make the defined timeout valid, else, mak

[PATCH v3 7/7] drivers: ddr: altera: Fix Cylcone5 SPL boot loop issue

Hardware watchdog configuration is handled correctly to resolve the SPL boot loop issue on Cyclone5. When hardware watchdog is enabled, it is reconfigured to make the defined timeout valid, else, making sure it is not running even if it is enabled in the preloader. Signed-off-by: Khairul Anuar Rom