On 10/4/24 9:16 AM, neil.armstr...@linaro.org wrote:
On 03/10/2024 15:19, Marek Vasut wrote:
On 10/3/24 2:49 PM, Neil Armstrong wrote:
On 02/10/2024 16:55, Marek Vasut wrote:
On 10/2/24 4:39 PM, Neil Armstrong wrote:
The current flush operation will omit doing a flush/invalidate on
the first
On 03/10/2024 15:19, Marek Vasut wrote:
On 10/3/24 2:49 PM, Neil Armstrong wrote:
On 02/10/2024 16:55, Marek Vasut wrote:
On 10/2/24 4:39 PM, Neil Armstrong wrote:
The current flush operation will omit doing a flush/invalidate on
the first and last bytes if the base address and size are not al
On 10/3/24 2:49 PM, Neil Armstrong wrote:
On 02/10/2024 16:55, Marek Vasut wrote:
On 10/2/24 4:39 PM, Neil Armstrong wrote:
The current flush operation will omit doing a flush/invalidate on
the first and last bytes if the base address and size are not aligned
with DMA_MINALIGN.
This causes ope
On 02/10/2024 16:55, Marek Vasut wrote:
On 10/2/24 4:39 PM, Neil Armstrong wrote:
The current flush operation will omit doing a flush/invalidate on
the first and last bytes if the base address and size are not aligned
with DMA_MINALIGN.
This causes operation failures Qualcomm platforms.
Take i
On 10/2/24 4:39 PM, Neil Armstrong wrote:
The current flush operation will omit doing a flush/invalidate on
the first and last bytes if the base address and size are not aligned
with DMA_MINALIGN.
This causes operation failures Qualcomm platforms.
Take in account the alignment and size of the b
The current flush operation will omit doing a flush/invalidate on
the first and last bytes if the base address and size are not aligned
with DMA_MINALIGN.
This causes operation failures Qualcomm platforms.
Take in account the alignment and size of the buffer and also
flush the previous and last c
6 matches
Mail list logo
