On Tue, Mar 07, 2023 at 06:30:19AM +, Conor Dooley wrote:
>
>
> On 7 March 2023 01:59:31 GMT, yanhong wang
> wrote:
> >
> >
> >On 2023/3/4 5:16, Conor Dooley wrote:
> >> On Fri, Mar 03, 2023 at 11:24:29AM +0800, Yanhong Wang wrote:
> >>> Add initial device tree for the JH7110 RISC-V SoC.
>
On 7 March 2023 01:59:31 GMT, yanhong wang
wrote:
>
>
>On 2023/3/4 5:16, Conor Dooley wrote:
>> On Fri, Mar 03, 2023 at 11:24:29AM +0800, Yanhong Wang wrote:
>>> Add initial device tree for the JH7110 RISC-V SoC.
>>>
>>> Signed-off-by: Yanhong Wang
>>> ---
>>> arch/riscv/dts/jh7110.dtsi | 5
On 2023/3/4 5:16, Conor Dooley wrote:
> On Fri, Mar 03, 2023 at 11:24:29AM +0800, Yanhong Wang wrote:
>> Add initial device tree for the JH7110 RISC-V SoC.
>>
>> Signed-off-by: Yanhong Wang
>> ---
>> arch/riscv/dts/jh7110.dtsi | 582 +
>> 1 file changed, 58
On Fri, Mar 03, 2023 at 11:24:29AM +0800, Yanhong Wang wrote:
> Add initial device tree for the JH7110 RISC-V SoC.
>
> Signed-off-by: Yanhong Wang
> ---
> arch/riscv/dts/jh7110.dtsi | 582 +
> 1 file changed, 582 insertions(+)
> create mode 100644 arch/riscv/
Add initial device tree for the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang
---
arch/riscv/dts/jh7110.dtsi | 582 +
1 file changed, 582 insertions(+)
create mode 100644 arch/riscv/dts/jh7110.dtsi
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh
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