Re: [PATCH v1 3/6] clk: microchip: mpfs: fix reference clock handling

> On Tue, 2022-10-25 at 08:58 +0100, Conor Dooley wrote: > The original devicetrees for PolarFire SoC messed up & defined the > msspll's output as a fixed-frequency, 600 MHz clock & used that as > the > input for the clock controller node. The msspll is not a fixed > frequency clock and later devic

Re: [PATCH v1 3/6] clk: microchip: mpfs: fix reference clock handling

On Tue, Oct 25, 2022 at 08:58:46AM +0100, Conor Dooley wrote: > The original devicetrees for PolarFire SoC messed up & defined the > msspll's output as a fixed-frequency, 600 MHz clock & used that as the > input for the clock controller node. The msspll is not a fixed > frequency clock and later de

[PATCH v1 3/6] clk: microchip: mpfs: fix reference clock handling

The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one o