On 1/6/21 2:10 PM, Marek Vasut wrote:
> On 1/6/21 10:06 PM, Stephen Warren wrote:
> [...]
>
> diff --git a/include/configs/tegra-common-post.h
> b/include/configs/tegra-common-post.h
> -#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
This is wrong; there
On 1/6/21 10:06 PM, Stephen Warren wrote:
[...]
diff --git a/include/configs/tegra-common-post.h
b/include/configs/tegra-common-post.h
-#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
This is wrong; there are other devices that are used on Tegra that
require the noncached me
On 1/6/21 1:53 PM, Marek Vasut wrote:
> On 1/6/21 8:25 PM, Stephen Warren wrote:
>> On 1/6/21 7:14 AM, Marek Vasut wrote:
>>> The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size
>>> words
>>> after the descriptor. Use this to pad the descriptors to cacheline
>>> size and
>>> remove
On 1/6/21 8:25 PM, Stephen Warren wrote:
On 1/6/21 7:14 AM, Marek Vasut wrote:
The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words
after the descriptor. Use this to pad the descriptors to cacheline size and
remove the need for noncached memory altogether. Moreover, this le
On 1/6/21 7:14 AM, Marek Vasut wrote:
> The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words
> after the descriptor. Use this to pad the descriptors to cacheline size and
> remove the need for noncached memory altogether. Moreover, this lets Tegra
> use the generic cache flush
The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words
after the descriptor. Use this to pad the descriptors to cacheline size and
remove the need for noncached memory altogether. Moreover, this lets Tegra
use the generic cache flush / invalidate operations.
Signed-off-by: Mare
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