On 2021/3/25 16:14, Stefano Babic wrote:
Hi Tim,
On 24.03.21 22:25, Tim Harvey wrote:
On Fri, Mar 19, 2021 at 12:31 AM Peng Fan (OSS)
wrote:
From: Ye Li
Users reported LPDDR4 MR12 value is set to 0 during PHY training,
not the value from FSP timing structure, which cause compliance test
Hi Tim,
On 24.03.21 22:25, Tim Harvey wrote:
On Fri, Mar 19, 2021 at 12:31 AM Peng Fan (OSS) wrote:
From: Ye Li
Users reported LPDDR4 MR12 value is set to 0 during PHY training,
not the value from FSP timing structure, which cause compliance test failed.
The root cause is the CATrainOpt[0]
On Fri, Mar 19, 2021 at 12:31 AM Peng Fan (OSS) wrote:
>
> From: Ye Li
>
> Users reported LPDDR4 MR12 value is set to 0 during PHY training,
> not the value from FSP timing structure, which cause compliance test failed.
> The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing
> but not
From: Ye Li
Users reported LPDDR4 MR12 value is set to 0 during PHY training,
not the value from FSP timing structure, which cause compliance test failed.
The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing
but not set in 1D. According to PHY training application node,
to enable the
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