On Sat, 29 Jan 2022 16:58:43 +0100
Jernej Skrabec wrote:
> Although it isn't known what bit 0 in PHY reg 8 does, it's obvious that
> it has to be set before read calibration and cleared afterwards. This is
> already done for first rank, but not for second (copy & paste error.)
Indeed looks like
Although it isn't known what bit 0 in PHY reg 8 does, it's obvious that
it has to be set before read calibration and cleared afterwards. This is
already done for first rank, but not for second (copy & paste error.)
Fix it.
Fixes: f4317dbd06b6 ("sunxi: Add H616 DRAM support")
Signed-off-by: Jernej
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