Re: [PATCH 2/2] spi: sunxi: fix clock divider calculation for max frequency setting

2024-07-16 Thread Michael Walle
> > - if ((div / 2) <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) { > > + if (div != 1 && ((div / 2) <= (SUN4I_CLK_CTL_CDR2_MASK + 1))) { > > div /= 2; > > This is still not fully correct, is it? If I ask for 10 MHz, the > algorithm should select 8 MHz (24/3) or actually 6 MHz (24/4), but it >

Re: [PATCH 2/2] spi: sunxi: fix clock divider calculation for max frequency setting

2024-07-15 Thread Andre Przywara
On Fri, 12 Jul 2024 19:14:57 +0200 Michael Walle wrote: Hi, > If the maximum frequency is requested, we still fall into the CDR2 > handling. But there the minimal divider is 2. For the sun6i and sun8i we > can do better with the CDR1 setting where the minimal divider is 1: > SPI_CLK = MOD_CLK

[PATCH 2/2] spi: sunxi: fix clock divider calculation for max frequency setting

2024-07-12 Thread Michael Walle
If the maximum frequency is requested, we still fall into the CDR2 handling. But there the minimal divider is 2. For the sun6i and sun8i we can do better with the CDR1 setting where the minimal divider is 1: SPI_CLK = MOD_CLK / 2 ^ cdr with cdr = 0 Thus, handle the div = 1 case specially. While