On Wed, Jul 13, 2022 at 10:59:45AM +0900, Kunihiko Hayashi wrote:
> UniPhier LD20, PXs2 and PXs3 boards have ethernet phy that has RX/TX delays
> of RGMII interface using pull-ups on the RXDLY and TXDLY pins.
>
> So should set the phy-mode to "rgmii-id" to show that RX/TX delays are
> enabled.
>
On Wed, Jul 13, 2022 at 4:59 AM Kunihiko Hayashi
wrote:
>
> UniPhier LD20, PXs2 and PXs3 boards have ethernet phy that has RX/TX delays
> of RGMII interface using pull-ups on the RXDLY and TXDLY pins.
>
> So should set the phy-mode to "rgmii-id" to show that RX/TX delays are
> enabled.
>
> Signed-
UniPhier LD20, PXs2 and PXs3 boards have ethernet phy that has RX/TX delays
of RGMII interface using pull-ups on the RXDLY and TXDLY pins.
So should set the phy-mode to "rgmii-id" to show that RX/TX delays are
enabled.
Signed-off-by: Kunihiko Hayashi
---
arch/arm/dts/uniphier-ld20.dtsi | 2 +-
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