Re: [PATCH 12/30] clk: renesas: Deduplicate gen3_clk_get_rate64() PLL handling

Hi Marek, Thank you for the patch. On Wed, Apr 28, 2021 at 8:33 PM Marek Vasut wrote: > > Most of the PLLx, MAIN, FIXED clock handlers are calling very similar > code, which determines parent rate and then applies multiplication and > division. The only difference is whether multiplication is fi

[PATCH 12/30] clk: renesas: Deduplicate gen3_clk_get_rate64() PLL handling

Most of the PLLx, MAIN, FIXED clock handlers are calling very similar code, which determines parent rate and then applies multiplication and division. The only difference is whether multiplication is fixed factor or coming from CRx register. Deduplicate the code into a single function. Signed-off-