Re: [PATCH 1/5] dts: stm32mp157c-odyssey: set PLL4_P to 125Mhz for ETH_CLK

2024-06-14 Thread Patrice CHOTARD
On 4/28/24 16:24, Heesub Shin wrote: > Odyssey board requires ETH_CLK of 125Mhz. This commit sets PLL4_P/Q/R to > 125, 62.5 and 62.5Mhz in respectively. > > Signed-off-by: Heesub Shin > --- > arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 delet

Re: [PATCH 1/5] dts: stm32mp157c-odyssey: set PLL4_P to 125Mhz for ETH_CLK

2024-06-06 Thread Patrice CHOTARD
On 4/28/24 16:24, Heesub Shin wrote: > Odyssey board requires ETH_CLK of 125Mhz. This commit sets PLL4_P/Q/R to > 125, 62.5 and 62.5Mhz in respectively. > > Signed-off-by: Heesub Shin > --- > arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 delet

[PATCH 1/5] dts: stm32mp157c-odyssey: set PLL4_P to 125Mhz for ETH_CLK

2024-04-28 Thread Heesub Shin
Odyssey board requires ETH_CLK of 125Mhz. This commit sets PLL4_P/Q/R to 125, 62.5 and 62.5Mhz in respectively. Signed-off-by: Heesub Shin --- arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/stm32mp157c-odyssey