Re: [PATCH 1/2] arch/riscv: add semihosting support for RISC-V

Hi Sean, Don't know about the DCSR.EBREAK option but it will be better for us to extend the existing trap vector functionality as you mentioned. Will handle this in v2. This also removes the need for us to implement our semihosting_enabled() in inline assembly as it will become a generic lib/semih

[PATCH 1/2] arch/riscv: add semihosting support for RISC-V

We add RISC-V semihosting based serial console for JTAG based early debugging. The RISC-V semihosting specification is available at: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc Signed-off-by: Anup Patel Signed-off-by: Kautuk Consul --- arch/riscv/Kconf

Re: [PATCH 1/2] arch/riscv: add semihosting support for RISC-V

Hi Kautuk, I've already noted my general remarks on this approach in response to your cover letter. This just has my comments on the RISC-V-specific parts. On 9/15/22 8:45 AM, Kautuk Consul wrote: > We add RISC-V semihosting based serial console for JTAG based early > debugging. > > The RISC-V s

Re: [PATCH 1/2] arch/riscv: add semihosting support for RISC-V

On Thu, Sep 15, 2022 at 6:15 PM Kautuk Consul wrote: > > We add RISC-V semihosting based serial console for JTAG based early > debugging. > > The RISC-V semihosting specification is available at: > https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc > > Signed-off