Hi Quentin,
On 2024/3/22 17:38, Quentin Schulz wrote:
Hi Kever,
On 2/19/24 10:50, Quentin Schulz wrote:
Hi Kever,
On 2/18/24 02:14, Kever Yang wrote:
Hi Quentin,
On 2024/2/9 21:18, Quentin Schulz wrote:
From: Quentin Schulz
The STM32_RST line is routed to the ATtiny microcontroller
PA0/RE
Hi Kever,
On 2/19/24 10:50, Quentin Schulz wrote:
Hi Kever,
On 2/18/24 02:14, Kever Yang wrote:
Hi Quentin,
On 2024/2/9 21:18, Quentin Schulz wrote:
From: Quentin Schulz
The STM32_RST line is routed to the ATtiny microcontroller
PA0/RESET/UPDI pin. By driving the PX30 SoC pin as GPIO output
Hi Kever,
On 2/18/24 02:14, Kever Yang wrote:
Hi Quentin,
On 2024/2/9 21:18, Quentin Schulz wrote:
From: Quentin Schulz
The STM32_RST line is routed to the ATtiny microcontroller
PA0/RESET/UPDI pin. By driving the PX30 SoC pin as GPIO output high, we
prevent external UPDI to be used for flash
Hi Quentin,
On 2024/2/9 21:18, Quentin Schulz wrote:
From: Quentin Schulz
The STM32_RST line is routed to the ATtiny microcontroller
PA0/RESET/UPDI pin. By driving the PX30 SoC pin as GPIO output high, we
prevent external UPDI to be used for flashing without first putting this
pin as GPIO input
From: Quentin Schulz
The STM32_RST line is routed to the ATtiny microcontroller
PA0/RESET/UPDI pin. By driving the PX30 SoC pin as GPIO output high, we
prevent external UPDI to be used for flashing without first putting this
pin as GPIO input, an extra step we could avoid in userspace.
There's a
5 matches
Mail list logo