Re: [PATCH] rockchip: clk: add UART0 clock getter/setter

Hi Quentin, I've submitted the updated version of the patch. Indeed the calculation for UART0_CLK_SEL_UART0_NP5 seemed wrong - I've corrected it. Added also casting to u64, as according to TRM, PLL can reach up to 3,2GHz. Declaration order and commit message are updated. As for the clock source for

Re: [PATCH] rockchip: clk: add UART0 clock getter/setter

Hi Lukasz, Maybe also make it explicit in the commit title that this is for px30 only :) On 8/1/24 12:26 PM, Quentin Schulz wrote: Hi Lukasz, On 7/31/24 11:43 AM, Lukasz Czechowski wrote: Add dedicated getter and setter for SCLK_UART0_PMU. This allows the driver to correctly handle UART0 cl

Re: [PATCH] rockchip: clk: add UART0 clock getter/setter

Hi Lukasz, On 7/31/24 11:43 AM, Lukasz Czechowski wrote: Add dedicated getter and setter for SCLK_UART0_PMU. This allows the driver to correctly handle UART0 clocks, and thus it fixes the issues with UART0 not working in case DEBUG_UART is disabled. Unlike other Rockchip SoCs, i.e. rk3399, in th

[PATCH] rockchip: clk: add UART0 clock getter/setter

Add dedicated getter and setter for SCLK_UART0_PMU. This allows the driver to correctly handle UART0 clocks, and thus it fixes the issues with UART0 not working in case DEBUG_UART is disabled. Unlike other Rockchip SoCs, i.e. rk3399, in the PX30 the default clock source for UART is GPLL, instead of