Maybe we should ask kernel people. It seems that Thomas Petazzoni may
be able to answer, since he is author of the following kernel patch:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f4ac99011e542d06ea2bda10063502583c6d7991
Hello Stefan!
On Monday 08 February 2021 15:19:20 Stefan Roese wrote:
> On 08.02.21 15:00, Marek Behun wrote:
> >I would like to know why this memory controller is there and whether
> >it should be configured. The pci-mvebu driver in kernel currently
> >ignores this Memory Controller.
Hi Marek,
On 08.02.21 15:00, Marek Behun wrote:
On Mon, 25 Jan 2021 15:25:31 +0100
Stefan Roese wrote:
This patch changes the PCI config routines in the Armada XP / 38x driver
to not allow access to the PCIe root ports.
While updating the Armada XP based theadorable to the latest mainline
an
On Mon, 25 Jan 2021 15:25:31 +0100
Stefan Roese wrote:
> This patch changes the PCI config routines in the Armada XP / 38x driver
> to not allow access to the PCIe root ports.
>
> While updating the Armada XP based theadorable to the latest mainline
> and testing it with the DM PCI driver I noti
On 25.01.21 15:25, Stefan Roese wrote:
This patch changes the PCI config routines in the Armada XP / 38x driver
to not allow access to the PCIe root ports.
While updating the Armada XP based theadorable to the latest mainline
and testing it with the DM PCI driver I noticed, that the PCI root
bri
This patch changes the PCI config routines in the Armada XP / 38x driver
to not allow access to the PCIe root ports.
While updating the Armada XP based theadorable to the latest mainline
and testing it with the DM PCI driver I noticed, that the PCI root
bridge was being configured incorrectly. Res
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