On Mon, 8 Feb 2021 16:49:58 +0100
Marek Vasut wrote:
Hi,
> On 2/8/21 2:32 PM, Andre Przywara wrote:
> [...]
> >>> +static void nvme_flush_dcache_range(void *start, unsigned long
> >>> size)
> >>> +{
> >>> + unsigned long s, e;
> >>> + nvme_ali
On 2/8/21 4:11 PM, Bin Meng wrote:
[...]
As I said: I don't see how this patch changes anything on arm64, which
the commit messages claims to be the reason for this post.
If someone please can confirm, but invalidate_dcache_range() always
works on arm64, in fact does the very rounding already tha
On 2/8/21 2:32 PM, Andre Przywara wrote:
[...]
+static void nvme_flush_dcache_range(void *start, unsigned long size)
+{
+ unsigned long s, e;
+ nvme_align_dcache_range(start, size, &s, &e);
+ flush_dcache_range(s, e);
There is no good reason for alignment restrictions when it
Hi Andre,
On Mon, Feb 8, 2021 at 9:33 PM Andre Przywara wrote:
>
> On Sun, 7 Feb 2021 14:13:37 -0500
> Tom Rini wrote:
>
> Hi Tom, Marek,
>
> > On Sun, Feb 07, 2021 at 07:20:14PM +0100, Marek Vasut wrote:
> > > On 2/4/21 5:57 PM, Tom Rini wrote:
> > > [...]
> > >
> > > > > > > > > > > +static vo
On Sun, 7 Feb 2021 14:13:37 -0500
Tom Rini wrote:
Hi Tom, Marek,
> On Sun, Feb 07, 2021 at 07:20:14PM +0100, Marek Vasut wrote:
> > On 2/4/21 5:57 PM, Tom Rini wrote:
> > [...]
> >
> > > > > > > > > > +static void nvme_flush_dcache_range(void *start, unsigned
> > > > > > > > > > long size)
>
On Sun, Feb 07, 2021 at 07:20:14PM +0100, Marek Vasut wrote:
> On 2/4/21 5:57 PM, Tom Rini wrote:
> [...]
>
> > > > > > > > > +static void nvme_flush_dcache_range(void *start, unsigned
> > > > > > > > > long size)
> > > > > > > > > +{
> > > > > > > > > + unsigned long s, e;
> > > > > > > >
On 2/4/21 5:57 PM, Tom Rini wrote:
[...]
+static void nvme_flush_dcache_range(void *start, unsigned long size)
+{
+ unsigned long s, e;
+ nvme_align_dcache_range(start, size, &s, &e);
+ flush_dcache_range(s, e);
There is no good reason for alignment restrictions when it comes
On Thu, Feb 04, 2021 at 10:26:36AM +, Andre Przywara wrote:
> On Wed, 3 Feb 2021 14:08:39 +0100
> Marek Vasut wrote:
>
> Hi Marek,
>
> I think our opinions actually don't differ that much, but we might be
> either misunderstanding ourselves or talk about different things.
> See below.
[snip]
On Wed, 3 Feb 2021 14:08:39 +0100
Marek Vasut wrote:
Hi Marek,
I think our opinions actually don't differ that much, but we might be
either misunderstanding ourselves or talk about different things.
See below.
> On 2/3/21 11:42 AM, Andre Przywara wrote:
>
> [...]
>
> >drivers/nvme/nvm
On 2/3/21 11:42 AM, Andre Przywara wrote:
[...]
drivers/nvme/nvme.c | 50 +
1 file changed, 32 insertions(+), 18 deletions(-)
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index 5d6331ad34..758415a53b 100644
--- a/drivers/nvme/nvme.c
++
On Tue, 2 Feb 2021 22:18:47 +0100
Marek Vasut wrote:
Hi,
> On 2/2/21 5:23 PM, Andre Przywara wrote:
> [...]
>
> >>> drivers/nvme/nvme.c | 50 +
> >>> 1 file changed, 32 insertions(+), 18 deletions(-)
> >>>
> >>> diff --git a/drivers/nvme/nvme.c b/d
On 2/2/21 5:23 PM, Andre Przywara wrote:
[...]
drivers/nvme/nvme.c | 50 +
1 file changed, 32 insertions(+), 18 deletions(-)
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index 5d6331ad34..758415a53b 100644
--- a/drivers/nvme/nvme.c
+++ b/
On Tue, 2 Feb 2021 11:55:50 +0800
Bin Meng wrote:
Hi,
had a look at the code, those are my findings:
> On Sun, Jan 31, 2021 at 1:53 AM Marek Vasut wrote:
> >
> > The various structures in the driver are already correcty padded and
>
> typo: correctly
>
> > cache aligned in memory, however
On 2/2/21 10:12 AM, Bin Meng wrote:
[...]
cache aligned in memory, however the cache operations are called on
the structure sizes, which themselves might not be cache aligned. Add
the necessary rounding to fix this, which permits the nvme to work on
arm64.
+ARM guys
Which ARM64 SoC did you tes
On 2/2/21 2:04 PM, Andre Przywara wrote:
Hi,
[...]
The various structures in the driver are already correcty padded and
typo: correctly
cache aligned in memory, however the cache operations are called on
the structure sizes, which themselves might not be cache aligned. Add
the necessary ro
On Tue, 2 Feb 2021 11:55:50 +0800
Bin Meng wrote:
Hi,
> On Sun, Jan 31, 2021 at 1:53 AM Marek Vasut wrote:
> >
> > The various structures in the driver are already correcty padded and
>
> typo: correctly
>
> > cache aligned in memory, however the cache operations are called on
> > the struc
On Tue, Feb 2, 2021 at 5:04 PM Marek Vasut wrote:
>
> On 2/2/21 9:54 AM, Bin Meng wrote:
> [...]
> cache aligned in memory, however the cache operations are called on
> the structure sizes, which themselves might not be cache aligned. Add
> the necessary rounding to fix this, which
On 2/2/21 9:54 AM, Bin Meng wrote:
[...]
cache aligned in memory, however the cache operations are called on
the structure sizes, which themselves might not be cache aligned. Add
the necessary rounding to fix this, which permits the nvme to work on
arm64.
+ARM guys
Which ARM64 SoC did you test
On Tue, Feb 2, 2021 at 4:05 PM Marek Vasut wrote:
>
> On 2/2/21 4:55 AM, Bin Meng wrote:
>
> Hi,
>
> >> The various structures in the driver are already correcty padded and
> >
> > typo: correctly
> >
> >> cache aligned in memory, however the cache operations are called on
> >> the structure sizes
On 2/2/21 4:55 AM, Bin Meng wrote:
Hi,
The various structures in the driver are already correcty padded and
typo: correctly
cache aligned in memory, however the cache operations are called on
the structure sizes, which themselves might not be cache aligned. Add
the necessary rounding to fix
On Sun, Jan 31, 2021 at 1:53 AM Marek Vasut wrote:
>
> The various structures in the driver are already correcty padded and
typo: correctly
> cache aligned in memory, however the cache operations are called on
> the structure sizes, which themselves might not be cache aligned. Add
> the necessar
The various structures in the driver are already correcty padded and
cache aligned in memory, however the cache operations are called on
the structure sizes, which themselves might not be cache aligned. Add
the necessary rounding to fix this, which permits the nvme to work on
arm64.
Signed-off-by:
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