Hi Marek,
On 25/10/21 10:25PM, Marek Vasut wrote:
> On 10/25/21 9:53 PM, Pratyush Yadav wrote:
> > On 08/10/21 06:06PM, Jagan Teki wrote:
> > > On Wed, Sep 15, 2021 at 2:05 PM Marek Vasut wrote:
> > > >
> > > > On 9/15/21 10:28 AM, Pratyush Yadav wrote:
> > > > > On 14/09/21 08:22PM, Marek Vasut
On Thu, Dec 2, 2021 at 11:20 AM Marek Vasut wrote:
>
> On 12/2/21 06:48, Jagan Teki wrote:
> > Hi Marek,
> >
> > On Tue, Sep 14, 2021 at 8:52 AM Marek Vasut wrote:
> >>
> >> Wait for the read/write transfer finish bit get actually cleared,
> >> this does not happen immediately on at least SoCFPGA
On 12/2/21 06:48, Jagan Teki wrote:
Hi Marek,
On Tue, Sep 14, 2021 at 8:52 AM Marek Vasut wrote:
Wait for the read/write transfer finish bit get actually cleared,
this does not happen immediately on at least SoCFPGA Gen5.
Signed-off-by: Marek Vasut
Cc: Jagan Teki
Cc: Vignesh R
Cc: Pratyus
Hi Marek,
On Tue, Sep 14, 2021 at 8:52 AM Marek Vasut wrote:
>
> Wait for the read/write transfer finish bit get actually cleared,
> this does not happen immediately on at least SoCFPGA Gen5.
>
> Signed-off-by: Marek Vasut
> Cc: Jagan Teki
> Cc: Vignesh R
> Cc: Pratyush Yadav
> ---
> drivers
Hi Pratyush,
On Tue, Oct 26, 2021 at 1:23 AM Pratyush Yadav wrote:
>
> On 08/10/21 06:06PM, Jagan Teki wrote:
> > On Wed, Sep 15, 2021 at 2:05 PM Marek Vasut wrote:
> > >
> > > On 9/15/21 10:28 AM, Pratyush Yadav wrote:
> > > > On 14/09/21 08:22PM, Marek Vasut wrote:
> > > >> On 9/14/21 7:42 PM,
On 10/25/21 9:53 PM, Pratyush Yadav wrote:
On 08/10/21 06:06PM, Jagan Teki wrote:
On Wed, Sep 15, 2021 at 2:05 PM Marek Vasut wrote:
On 9/15/21 10:28 AM, Pratyush Yadav wrote:
On 14/09/21 08:22PM, Marek Vasut wrote:
On 9/14/21 7:42 PM, Pratyush Yadav wrote:
On 14/09/21 05:22AM, Marek Vasut
On 08/10/21 06:06PM, Jagan Teki wrote:
> On Wed, Sep 15, 2021 at 2:05 PM Marek Vasut wrote:
> >
> > On 9/15/21 10:28 AM, Pratyush Yadav wrote:
> > > On 14/09/21 08:22PM, Marek Vasut wrote:
> > >> On 9/14/21 7:42 PM, Pratyush Yadav wrote:
> > >>> On 14/09/21 05:22AM, Marek Vasut wrote:
> > Wai
On Wed, Sep 15, 2021 at 2:05 PM Marek Vasut wrote:
>
> On 9/15/21 10:28 AM, Pratyush Yadav wrote:
> > On 14/09/21 08:22PM, Marek Vasut wrote:
> >> On 9/14/21 7:42 PM, Pratyush Yadav wrote:
> >>> On 14/09/21 05:22AM, Marek Vasut wrote:
> Wait for the read/write transfer finish bit get actually
On 9/15/21 10:28 AM, Pratyush Yadav wrote:
On 14/09/21 08:22PM, Marek Vasut wrote:
On 9/14/21 7:42 PM, Pratyush Yadav wrote:
On 14/09/21 05:22AM, Marek Vasut wrote:
Wait for the read/write transfer finish bit get actually cleared,
this does not happen immediately on at least SoCFPGA Gen5.
Sig
On 14/09/21 08:22PM, Marek Vasut wrote:
> On 9/14/21 7:42 PM, Pratyush Yadav wrote:
> > On 14/09/21 05:22AM, Marek Vasut wrote:
> > > Wait for the read/write transfer finish bit get actually cleared,
> > > this does not happen immediately on at least SoCFPGA Gen5.
> > >
> > > Signed-off-by: Marek
On 9/14/21 7:42 PM, Pratyush Yadav wrote:
On 14/09/21 05:22AM, Marek Vasut wrote:
Wait for the read/write transfer finish bit get actually cleared,
this does not happen immediately on at least SoCFPGA Gen5.
Signed-off-by: Marek Vasut
Cc: Jagan Teki
Cc: Vignesh R
Cc: Pratyush Yadav
---
dri
On 14/09/21 05:22AM, Marek Vasut wrote:
> Wait for the read/write transfer finish bit get actually cleared,
> this does not happen immediately on at least SoCFPGA Gen5.
>
> Signed-off-by: Marek Vasut
> Cc: Jagan Teki
> Cc: Vignesh R
> Cc: Pratyush Yadav
> ---
> drivers/spi/cadence_qspi_apb.c
Wait for the read/write transfer finish bit get actually cleared,
this does not happen immediately on at least SoCFPGA Gen5.
Signed-off-by: Marek Vasut
Cc: Jagan Teki
Cc: Vignesh R
Cc: Pratyush Yadav
---
drivers/spi/cadence_qspi_apb.c | 17 +
1 file changed, 17 insertions(+)
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