Re: [PATCH] mmc: zynq_sdhci: Fix SDx_BASECLK configuration

2022-03-29 Thread Michal Simek
pá 25. 3. 2022 v 13:11 odesílatel Michal Simek napsal: > > From: Ashok Reddy Soma > > The DLL mode supported SD reference clocks are 50 MHz, 100 MHz and > 200 MHz. When user select SD frequency as 200MHz in the design, the > actual frequency is going to come around ~187MHz (<= 200MHz considering

Re: [PATCH] mmc: zynq_sdhci: Fix SDx_BASECLK configuration

2022-03-28 Thread Jaehoon Chung
On 3/25/22 21:11, Michal Simek wrote: > From: Ashok Reddy Soma > > The DLL mode supported SD reference clocks are 50 MHz, 100 MHz and > 200 MHz. When user select SD frequency as 200MHz in the design, the > actual frequency is going to come around ~187MHz (<= 200MHz considering > the parent clock

[PATCH] mmc: zynq_sdhci: Fix SDx_BASECLK configuration

2022-03-25 Thread Michal Simek
From: Ashok Reddy Soma The DLL mode supported SD reference clocks are 50 MHz, 100 MHz and 200 MHz. When user select SD frequency as 200MHz in the design, the actual frequency is going to come around ~187MHz (<= 200MHz considering the parent clock and divisor selection). We need to set SDx_BASECLK