Re: [PATCH] mmc: meson_gx_mmc: control ddr_mode bit

2020-11-10 Thread Mark Kettenis
> From: Jaehoon Chung > Date: Tue, 10 Nov 2020 18:02:02 +0900 > > On 11/10/20 5:50 PM, Mark Kettenis wrote: > >> From: Neil Armstrong > >> Date: Tue, 10 Nov 2020 09:15:14 +0100 > >> > >> On 10/11/2020 08:50, Jaehoon Chung wrote: > >>> EMMC_CFG register has a cfg_ddr bit(BIT[2]). > >>> It needs t

Re: [PATCH] mmc: meson_gx_mmc: control ddr_mode bit

2020-11-10 Thread Jaehoon Chung
On 11/10/20 5:50 PM, Mark Kettenis wrote: >> From: Neil Armstrong >> Date: Tue, 10 Nov 2020 09:15:14 +0100 >> >> On 10/11/2020 08:50, Jaehoon Chung wrote: >>> EMMC_CFG register has a cfg_ddr bit(BIT[2]). >>> It needs to set when mmc is running to ddr mode. >>> Otherwise, its bit should be cleared.

Re: [PATCH] mmc: meson_gx_mmc: control ddr_mode bit

2020-11-10 Thread Mark Kettenis
> From: Neil Armstrong > Date: Tue, 10 Nov 2020 09:15:14 +0100 > > On 10/11/2020 08:50, Jaehoon Chung wrote: > > EMMC_CFG register has a cfg_ddr bit(BIT[2]). > > It needs to set when mmc is running to ddr mode. > > Otherwise, its bit should be cleared. > > CFG_DDR[2] - 1: DDR mode, 0: SDR mode >

Re: [PATCH] mmc: meson_gx_mmc: control ddr_mode bit

2020-11-10 Thread Jaehoon Chung
On 11/10/20 5:15 PM, Neil Armstrong wrote: > On 10/11/2020 08:50, Jaehoon Chung wrote: >> EMMC_CFG register has a cfg_ddr bit(BIT[2]). >> It needs to set when mmc is running to ddr mode. >> Otherwise, its bit should be cleared. >> CFG_DDR[2] - 1: DDR mode, 0: SDR mode >> >> Signed-off-by: Jaehoon C

Re: [PATCH] mmc: meson_gx_mmc: control ddr_mode bit

2020-11-10 Thread Neil Armstrong
On 10/11/2020 08:50, Jaehoon Chung wrote: > EMMC_CFG register has a cfg_ddr bit(BIT[2]). > It needs to set when mmc is running to ddr mode. > Otherwise, its bit should be cleared. > CFG_DDR[2] - 1: DDR mode, 0: SDR mode > > Signed-off-by: Jaehoon Chung > --- > arch/arm/include/asm/arch-meson/sd_

[PATCH] mmc: meson_gx_mmc: control ddr_mode bit

2020-11-09 Thread Jaehoon Chung
EMMC_CFG register has a cfg_ddr bit(BIT[2]). It needs to set when mmc is running to ddr mode. Otherwise, its bit should be cleared. CFG_DDR[2] - 1: DDR mode, 0: SDR mode Signed-off-by: Jaehoon Chung --- arch/arm/include/asm/arch-meson/sd_emmc.h | 1 + drivers/mmc/meson_gx_mmc.c|