On Wed, Aug 30, 2023 at 12:32:30PM +0100, Andre Przywara wrote:
> The ARMv8.5 architecture extension defines architectural RNDR/RNDRRS
> system registers, that provide 64 bits worth of randomness on every
> read. Since it's an extension, and implementing it is optional, there is
> a field in the I
On Thu, 31 Aug 2023 13:01:57 -0600
Simon Glass wrote:
Hi Simon,
> On Thu, 31 Aug 2023 at 06:43, Andre Przywara wrote:
> >
> > On Wed, 30 Aug 2023 20:49:18 -0600
> > Simon Glass wrote:
> >
> > Hi Simon,
> >
> > > On Wed, 30 Aug 2023 at 05:32, Andre Przywara
> > > wrote:
> > > >
> > > > Th
Hi Andre,
On Thu, 31 Aug 2023 at 06:43, Andre Przywara wrote:
>
> On Wed, 30 Aug 2023 20:49:18 -0600
> Simon Glass wrote:
>
> Hi Simon,
>
> > On Wed, 30 Aug 2023 at 05:32, Andre Przywara wrote:
> > >
> > > The ARMv8.5 architecture extension defines architectural RNDR/RNDRRS
> > > system registe
On Wed, 30 Aug 2023 20:49:18 -0600
Simon Glass wrote:
Hi Simon,
> On Wed, 30 Aug 2023 at 05:32, Andre Przywara wrote:
> >
> > The ARMv8.5 architecture extension defines architectural RNDR/RNDRRS
> > system registers, that provide 64 bits worth of randomness on every
> > read. Since it's an exte
Hi Andre,
On Wed, 30 Aug 2023 at 05:32, Andre Przywara wrote:
>
> The ARMv8.5 architecture extension defines architectural RNDR/RNDRRS
> system registers, that provide 64 bits worth of randomness on every
> read. Since it's an extension, and implementing it is optional, there is
> a field in the
The ARMv8.5 architecture extension defines architectural RNDR/RNDRRS
system registers, that provide 64 bits worth of randomness on every
read. Since it's an extension, and implementing it is optional, there is
a field in the ID_AA64ISAR0_EL1 ID register to query the availability
of those registers.
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