Re: [PATCH] arm: mxs: Clear CPSR V bit to activate low vectors

Hi Marek, Lukasz, On 31.07.23 10:06, Lukasz Majewski wrote: On Sat, 29 Jul 2023 15:30:10 +0200 Marek Vasut wrote: The MXS starts with CPSR V bit set, which makes the CPU jump to high vectors in case of an exception. Those high vectors are located at 0x, which is where the BootROM exce

Re: [PATCH] arm: mxs: Clear CPSR V bit to activate low vectors

On Sat, 29 Jul 2023 15:30:10 +0200 Marek Vasut wrote: > The MXS starts with CPSR V bit set, which makes the CPU jump to high > vectors in case of an exception. Those high vectors are located at > 0x, which is where the BootROM exception table is located as > well. U-Boot should handle exc

[PATCH] arm: mxs: Clear CPSR V bit to activate low vectors

The MXS starts with CPSR V bit set, which makes the CPU jump to high vectors in case of an exception. Those high vectors are located at 0x, which is where the BootROM exception table is located as well. U-Boot should handle exceptions on its own using its own exception handling code, which