On 16/07/20 2:32 am, Andrew F. Davis wrote:
> When switching on or off the ARM caches some care must be taken to ensure
> existing cache line allocations are not left in an inconsistent state.
> An example of this is when cache lines are considered non-shared by
> and L3 controller even though t
When switching on or off the ARM caches some care must be taken to ensure
existing cache line allocations are not left in an inconsistent state.
An example of this is when cache lines are considered non-shared by
and L3 controller even though the lines are shared. To prevent these
and other issues
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