Hi Marek,
> From: Marek Vasut
> Sent: samedi 22 août 2020 22:45
>
> PLL4Q is supplying both FDCAN and LTDC. In case HDMI is in use, the
> 50 MHz generated from PLL4Q cannot be divided well enough to produce accurate
> clock for HDMI pixel clock. Adjust it to generate 74.25 MHz instead. The
> PLL
PLL4Q is supplying both FDCAN and LTDC. In case HDMI is in use, the
50 MHz generated from PLL4Q cannot be divided well enough to produce
accurate clock for HDMI pixel clock. Adjust it to generate 74.25 MHz
instead. The PLL4P/PLL4R are generating 99 MHz instead of 100 MHz,
which is in tolerance for
The PLL4 is supplying SDMMC12, SDMMC3 and SPDIF with 120 MHz and
FDCAN with 96 MHz. This isn't good for the SDMMC interfaces, which
can not easily divide the clock down to e.g. 50 MHz for high speed
SD and eMMC devices, so those devices end up running at 30 MHz as
that is 120 MHz / 4. Adjust the PL
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