Re: [U-Boot] [PATCH] powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs

, (0x80400020) Clock Configuration: + CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz, + DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz, + DSP CPU4:1200 MHz, DSP CPU5:1200 MHz, + CCB:666.667 MHz, + DDR:933.333 MHz (1866.667 MT/s

Re: [U-Boot] [PATCH] powerpc/mpc85xx: Enabling CPC conditionally based on hwconfig options

Hi York, This change was required to provide the flexibility of enabling DDRC1/CPC1 by SC3900/DSP core as DDRC1 is used by Starcore. SC enables CPC1 as per their requirement. PPC core use DDRC2, so it enables DDRC2/CPC2. Do you suggest mentioning it in the commit message also? Thanks and Regard

Re: [U-Boot] [PATCH] fsl_i2c: Add write-then-read transaction interface for I2C slave

-Original Message- From: Sun York-R58495 Sent: Saturday, March 08, 2014 3:10 AM To: Leekha Shaveta-B20052; u-boot@lists.denx.de Cc: Aggrwal Poonam-B10812; Aggrwal Poonam-B10812 Subject: Re: [PATCH] fsl_i2c: Add write-then-read transaction interface for I2C slave On 03/03/2014 12:58 AM,