From: Haibo Chen
Current code use dm_gpio_get_value() to get SDA and SCL value, and the
value depends on whether DTS file config the GPIO_ACTIVE_LOW. In ususal
case for i2c GPIO, DTS need to set GPIO_ACTIVE_LOW for SCL/SDA pins. So
here the logic is not correct.
And we must not use
From: Haibo Chen
dm_gpio_set_dir_flags() will clear GPIOD_MASK_DIR and set new flags.
But there are cases like i2c_deblock_gpio_loop() will do like this:
-first conifg GPIO(SDA) output with GPIOD_ACTIVE_LOW
dm_gpio_set_dir_flags(pin, GPIOD_IS_OUT |
GPIOD_ACTIVE_LOW
From: Haibo Chen
Current code use dm_gpio_get_value() to get SDA and SCL value, and the
value depends on the flag GPIOD_ACTIVE_LOW. When toggle SCL to wait
slave release SDA, the SDA are config as GPIOD_IS_IN, and whether contain
the GPIOD_ACTIVE_LOW depends on the DTS setting. Usually, for I2C
From: Haibo Chen
After commit f132aab40327 ("Revert "mmc: fsl_esdhc_imx: use
VENDORSPEC_FRC_SDCLK_ON to control card clock output""), it
involve issue in mmc_switch_voltage(), because of the special
design of usdhc.
For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HC
From: Haibo Chen
Now original fsl_esdhc.c are split as fsl_esdhc.c and fsl_esdhc_imx.c.
fsl_esdhc_imx.c only cover i.MX SoC. So ARCH_MXC is redundant.
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 15 +++
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a
From: Haibo Chen
The original code logic can not show the correct card clock, and also
has one risk when the div is 0. Because there is div -=1 before.
So move the operation before div -=1, and also involve ddr_pre_div
to get the correct value.
Signed-off-by: Haibo Chen
---
drivers/mmc
From: Haibo Chen
After commit f132aab40327 ("Revert "mmc: fsl_esdhc_imx: use
VENDORSPEC_FRC_SDCLK_ON to control card clock output""), it
involve issue in mmc_switch_voltage(), because of the special
design of usdhc.
For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HC
From: Haibo Chen
Some board like imx8mm-evkb, IO voltage switch from 3.3v to 1.8v need
around 18ms, common code only delay 10ms, so need to delay extra 8ms.
Otherwise voltage switch will timeout when wait for data0 line.
This IO voltage switch time depends on board design, depend on the
PMIC
From: Haibo Chen
Common code already handle the voltage switch sequence based on spec,
so remove the redundant voltage switch code.
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc
From: Haibo Chen
Common code already handle the voltage switch sequence based on spec,
so remove the redundant voltage switch code.
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/mmc
From: Haibo Chen
For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these
are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the
card clock output.
After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support"),
we meet SD3.0 card can
From: Haibo Chen
For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these
are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the
card clock output.
After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support"),
we meet SD3.0 card can
From: Haibo Chen
Add wait_dat0() support, upper layer will use this callback.
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 22040c67a8..29592d1f2c
From: Haibo Chen
For imx usdhc/esdhc, once set the DDR_EN, enable the DDR mode, the
card clock will be divied by 2 automatically by the host. So need
to first config the DDR_EN correctly, then update the card clock.
This will make sure the actual card clock is as our expected.
IC also suggest
From: Haibo Chen
Add wait_dat0() support, upper layer will use this callback.
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 22040c67a8
From: Haibo Chen
Add wait_dat0() support, upper layer will use this callback.
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 22040c67a8
From: Haibo Chen
Currently, readl/writel and esdhc_read32/esdhc_write32 are used. To align
the usage, change to only use esdhc_read32/esdhc_write32.
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 64 ++---
1 file changed, 32 insertions(+), 32
From: Haibo Chen
This 1ms delay before sending command already exist from the beginning
of the fsl_esdhc driver added in year 2008. Now this driver has been
split for two files: fsl_esdhc.c and fsl_esdhc_imx.c. fsl_esdhc_imx.c
only for i.MX series. i.MX series esdhc/usdhc do not need this 1ms
From: Haibo Chen
According to the code logic in __mmc_switch, if the parameter 'send_status'
is zero, no need to send cmd13, just wait the stated timeout time, then
can return directly.
Signed-off-by: Haibo Chen
---
drivers/mmc/mmc.c | 4 +++-
1 file changed, 3 insertions(+),
From: Haibo Chen
Currently, after config the clock rate, delay 10ms, this is quite a rough
method. Check the clock stable status in the present status register is
enough.
Tested-by: Ji Luo
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 7 ++-
1 file changed, 6 insertions
From: Haibo Chen
Currently, readl/writel and esdhc_read32/esdhc_write32 are used. To align
the usage, change to only use esdhc_read32/esdhc_write32.
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 64 ++---
1 file changed, 32 insertions(+), 32
From: Haibo Chen
Currently, after config the clock rate, delay 10ms, this is quite a rough
method. Check the clock stable status in the present status register is
enough.
Tested-by: Ji Luo
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 7 ++-
1 file changed, 6 insertions
From: Haibo Chen
Currently, after config the clock rate, delay 10ms, this is quite a rough
method. Check the clock stable status in the present status register is
enough.
Tested-by: Ji Luo
Signed-off-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 10 +-
1 file changed, 9 insertions
From: Haibo Chen
According the RM, the bit[6~0] of register ESDHC_TUNING_CTRL is
TUNING_START_TAP, bit[7] of this register is to disable the command
CRC check for standard tuning. So fix it here.
Fixes: fa33d207494c ("mmc: split fsl_esdhc driver for i.MX")
Signed-off-by:
From: Haibo Chen
In current code, we add 1ms dealy after each tuning command for standard
tuning method. Adding this 1ms dealy is because USDHC default check the
CMD CRC and DATA line. If detect the CMD CRC, USDHC standard tuning
IC logic do not wait for the tuning data sending out by the card
From: Haibo Chen
According to eMMC specification v5.1 section 6.4.3, we should issue
CMD1 repeatedly in the idle state until the eMMC is ready even if
mmc_send_op_cond() send CMD1 with argument = 0. Otherwise some eMMC
devices seems to enter the inactive mode after mmc_complete_op_cond()
issued
From: Haibo Chen
According to eMMC specification v5.1 section 6.4.3, we should issue
CMD1 repeatedly in the idle state until the eMMC is ready even if
mmc_send_op_cond() send CMD1 with argument = 0. Otherwise some eMMC
devices seems to enter the inactive mode after mmc_complete_op_cond()
issued
r bits of the result will all be 1.
Thanks to coverity <http://www.coverity.com>
e.g.
u8 data_8;
u64 data_64;
data_8 = 0x80;
data_64 = data_8 << 24; //0x8000
data_64 = ((u64)data_8) << 24; //0x8000
Signed-off-by:
28 matches
Mail list logo
