[PATCHv5 14/14] configs: imx93: enable the 'cpu' command

From: Hou Zhiqiang Enable the 'cpu' command to display the CPU info and release CPU core to run baremetal or RTOS applications. Signed-off-by: Hou Zhiqiang --- V5: - No change. configs/imx93_11x11_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx93_11x11_evk_defco

[PATCHv5 13/14] configs: imx8m: enable the 'cpu' command

From: Hou Zhiqiang Enable the 'cpu' command and the depended imx CPU driver to display the CPU info and release CPU core to run baremetal or RTOS applications. Signed-off-by: Hou Zhiqiang --- V5: - No change. configs/imx8mm_evk_defconfig | 3 +++ configs/imx8mn_evk_defconfig | 3 +++ configs

[PATCHv5 12/14] MAINTAINERS: add entry for cpu command

From: Hou Zhiqiang Added the original author Simon and myself. Signed-off-by: Hou Zhiqiang Reviewed-by: Simon Glass --- V5: - No change. MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c2832345ab..ddcb7128db 100644 --- a/MAINTAINERS +++

[PATCHv5 11/14] doc: cmd: add documentation for cpu command

From: Hou Zhiqiang Add documentation for the 'cpu' command, taking NXP i.MX 8M Plus as a example. Signed-off-by: Hou Zhiqiang Reviewed-by: Simon Glass --- V5: - Added cmd/cpu to doc/usage/index.rst to fix doc build failure. doc/usage/cmd/cpu.rst | 101 +++

[PATCHv5 10/14] cmd: cpu: add release subcommand

From: Hou Zhiqiang Add a new subcommand 'release' to bring up a core to run baremetal and RTOS applications. For example on i.MX8M Plus EVK, release the LAST core to run a RTOS application, passing the sequence number of the CPU core to release, here it is 3: u-boot=> cpu list 0: cpu@0

[PATCHv5 09/14] cpu: imx: implement release_core callback

From: Hou Zhiqiang Release the secondary cores through the PSCI request. Signed-off-by: Hou Zhiqiang --- V5: - No change. drivers/cpu/imx8_cpu.c | 24 1 file changed, 24 insertions(+) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index a35147b72a..60d

[PATCHv5 08/14] cpu: imx: Add i.MX 8M series SoCs

From: Hou Zhiqiang Add i.MX 8M Mini, Nano and Plus SoCs support. Signed-off-by: Hou Zhiqiang --- V5: - No change. drivers/cpu/imx8_cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index b633a2c73a..a35147b72a 100644 --- a/drivers

[PATCHv5 07/14] cpu: imx: removed the tail '\n' of the CPU description

From: Hou Zhiqiang Return CPU description string without newline character in the end. Signed-off-by: Hou Zhiqiang --- V5: - No change. drivers/cpu/imx8_cpu.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 6a97b7b9ad..b633a2c73a 100

[PATCHv5 06/14] cpu: imx: fix the CPU type field width

From: Hou Zhiqiang Increase one more bit to cover all CPU types. Otherwise it shows wrong CPU info on some platforms, such as i.MX8M Plus: U-Boot 2024.04+g674440bc73e+p0 (Jun 06 2024 - 10:05:34 +) CPU: NXP i.MX8MM Rev1.1 A53 at 4154504685 MHz at 30C Model: NXP i.MX8MPlus LPDD

[PATCHv5 05/14] cpu: imx: fix the CPU frequency in cpu_imx_get_info()

From: Hou Zhiqiang The cpu_freq stores the current CPU frequency in Hz. Signed-off-by: Hou Zhiqiang Reviewed-by: Michael Trimarchi --- V5: - No change. drivers/cpu/imx8_cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cp

[PATCHv5 04/14] test: cpu: add test for release CPU core.

From: Hou Zhiqiang Add test for API cpu_release_core(). Signed-off-by: Hou Zhiqiang Reviewed-by: Simon Glass --- V5: - No change. test/dm/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/test/dm/cpu.c b/test/dm/cpu.c index acba810599..8af25316ce 100644 --- a/test/dm/cpu.c +++ b/t

[PATCHv5 03/14] cpu: sandbox: implement release_core callback

From: Hou Zhiqiang Add empty release CPU core function for testing. Signed-off-by: Hou Zhiqiang Reviewed-by: Simon Glass --- V5: - No change. drivers/cpu/cpu_sandbox.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/cpu/cpu_sandbox.c b/drivers/cpu/cpu_sandbox.c index e65e1

[PATCHv5 02/14] cpu: add release_core callback

From: Hou Zhiqiang Add a new callback release_core to the cpu_ops, which is used to release a CPU core to run baremetal or RTOS application on a SoC with multiple CPU cores. Signed-off-by: Hou Zhiqiang Reviewed-by: Simon Glass --- V5: - No change. drivers/cpu/cpu-uclass.c | 10 ++ i

[PATCHv5 01/14] clk: imx8m: register ARM A53 core clock

From: Hou Zhiqiang Register ARM A53 core clock for i.MX 8M Mini, Nano and Plus, preparing for enabling the 'cpu' command, which depends on this to print CPU core frequency. Signed-off-by: Hou Zhiqiang --- V5: - Made the i.MX8M core clock CLK_IS_CRITICAL. drivers/clk/imx/clk-imx8mm.c | 8

[PATCHv5 00/14] Add a subcommand 'release' to cmd/cpu.c

From: Hou Zhiqiang This patch set is to add a subcommand 'release' to the 'cpu' command in cmd/cpu.c, making the command is able to release a core to run baremetal and RTOS applications. Fixed some problems of the imx8_cpu.c and added i.MX 8M series SoCs support. Added ARM A53 core clock regist

[PATCHv4 14/14] configs: imx93: enable the 'cpu' command

From: Hou Zhiqiang Enable the 'cpu' command to display the CPU info and release CPU core to run baremetal or RTOS applications. Signed-off-by: Hou Zhiqiang --- V4: - No change. configs/imx93_11x11_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx93_11x11_evk_defco

[PATCHv4 13/14] configs: imx8m: enable the 'cpu' command

From: Hou Zhiqiang Enable the 'cpu' command and the depended imx CPU driver to display the CPU info and release CPU core to run baremetal or RTOS applications. Signed-off-by: Hou Zhiqiang --- V4: - No change. configs/imx8mm_evk_defconfig | 3 +++ configs/imx8mn_evk_defconfig | 3 +++ configs

[PATCHv4 12/14] MAINTAINERS: add entry for cpu command

From: Hou Zhiqiang Added the original author Simon and myself. Signed-off-by: Hou Zhiqiang --- V4: - No change. MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a6e47e8a21..f1aa802758 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -996,6 +

[PATCHv4 11/14] doc: cmd: add documentation for cpu command

From: Hou Zhiqiang Add documentation for the 'cpu' command, taking NXP i.MX 8M Plus as a example. Signed-off-by: Hou Zhiqiang --- V4: - Added brief descriptions for each subcommand.. doc/usage/cmd/cpu.rst | 101 ++ 1 file changed, 101 insertions(+) cr

[PATCHv4 10/14] cmd: cpu: add release subcommand

From: Hou Zhiqiang Add a new subcommand 'release' to bring up a core to run baremetal and RTOS applications. For example on i.MX8M Plus EVK, release the LAST core to run a RTOS application, passing the sequence number of the CPU core to release, here it is 3: u-boot=> cpu list 0: cpu@0

[PATCHv4 09/14] cpu: imx: implement release_core callback

From: Hou Zhiqiang Release the secondary cores through the PSCI request. Signed-off-by: Hou Zhiqiang --- V4: - No change. drivers/cpu/imx8_cpu.c | 24 1 file changed, 24 insertions(+) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index a35147b72a..60d

[PATCHv4 08/14] cpu: imx: Add i.MX 8M series SoCs

From: Hou Zhiqiang Add i.MX 8M Mini, Nano and Plus SoCs support. Signed-off-by: Hou Zhiqiang --- V4: - No change. drivers/cpu/imx8_cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index b633a2c73a..a35147b72a 100644 --- a/drivers

[PATCHv4 07/14] cpu: imx: removed the tail '\n' of the CPU description

From: Hou Zhiqiang Return CPU description string without newline character in the end. Signed-off-by: Hou Zhiqiang --- V4: - New patch. drivers/cpu/imx8_cpu.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 6a97b7b9ad..b633a2c73a 100

[PATCHv4 06/14] cpu: imx: fix the CPU type field width

From: Hou Zhiqiang Increase one more bit to cover all CPU types. Otherwise it shows wrong CPU info on some platforms, such as i.MX8M Plus: U-Boot 2024.04+g674440bc73e+p0 (Jun 06 2024 - 10:05:34 +) CPU: NXP i.MX8MM Rev1.1 A53 at 4154504685 MHz at 30C Model: NXP i.MX8MPlus LPDD

[PATCHv4 05/14] cpu: imx: fix the CPU frequency in cpu_imx_get_info()

From: Hou Zhiqiang The cpu_freq stores the current CPU frequency in Hz. Signed-off-by: Hou Zhiqiang --- V4: - Rewrote the change log. drivers/cpu/imx8_cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 4781a5655

[PATCHv4 04/14] test: cpu: add test for release CPU core.

From: Hou Zhiqiang Add test for API cpu_release_core(). Signed-off-by: Hou Zhiqiang Reviewed-by: Simon Glass --- V4: - No change. test/dm/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/test/dm/cpu.c b/test/dm/cpu.c index acba810599..8af25316ce 100644 --- a/test/dm/cpu.c +++ b/t

[PATCHv4 03/14] cpu: sandbox: implement release_core callback

From: Hou Zhiqiang Add empty release CPU core function for testing. Signed-off-by: Hou Zhiqiang Reviewed-by: Simon Glass --- V4: - No change. drivers/cpu/cpu_sandbox.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/cpu/cpu_sandbox.c b/drivers/cpu/cpu_sandbox.c index e65e1

[PATCHv4 02/14] cpu: add release_core callback

From: Hou Zhiqiang Add a new callback release_core to the cpu_ops, which is used to release a CPU core to run baremetal or RTOS application on a SoC with multiple CPU cores. Signed-off-by: Hou Zhiqiang Reviewed-by: Simon Glass --- V4: - No change. drivers/cpu/cpu-uclass.c | 10 ++ i

[PATCHv4 01/14] clk: imx8m: register ARM A53 core clock

From: Hou Zhiqiang Register ARM A53 core clock for i.MX 8M Mini, Nano and Plus, preparing for enabling the 'cpu' command, which depends on this to print CPU core frequency. Signed-off-by: Hou Zhiqiang --- V4: - Moved here from other thread. drivers/clk/imx/clk-imx8mm.c | 6 ++ drivers/cl

[PATCHv3 00/14] Add a subcommand 'release' to cmd/cpu.c

From: Hou Zhiqiang This patch set is to add a subcommand 'release' to the 'cpu' command in cmd/cpu.c, making the command is able to release a core to run baremetal and RTOS applications. Fixed some problems of the imx8_cpu.c and added i.MX 8M series SoCs support. Added ARM A53 core clock regist

[PATCHv3 12/12] configs: imx93: enable the 'cpu' command

From: Hou Zhiqiang Enable the 'cpu' command to display the CPU info and release CPU core to run baremetal or RTOS applications. Signed-off-by: Hou Zhiqiang --- V3: - No change. configs/imx93_11x11_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx93_11x11_evk_defco

[PATCHv3 11/12] configs: imx8m: enable the 'cpu' command

From: Hou Zhiqiang Enable the 'cpu' command and the depended imx CPU driver to display the CPU info and release CPU core to run baremetal or RTOS applications. Signed-off-by: Hou Zhiqiang --- V3: - No change. configs/imx8mm_evk_defconfig | 3 +++ configs/imx8mn_evk_defconfig | 3 +++ configs

[PATCHv3 10/12] MAINTAINERS: add entry for cpu command

From: Hou Zhiqiang Added the original author Simon and myself. Signed-off-by: Hou Zhiqiang --- V3: - New patch. MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a6e47e8a217..f1aa802758d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -996,6

[PATCHv3 09/12] doc: cmd: add documentation for cpu command

From: Hou Zhiqiang Add documentation for the 'cpu' command, taking NXP i.MX 8M Plus as a example. Signed-off-by: Hou Zhiqiang --- V3: - New patch. doc/usage/cmd/cpu.rst | 82 +++ 1 file changed, 82 insertions(+) create mode 100644 doc/usage/cmd/cpu.rs

[PATCHv3 07/12] cpu: imx: implement release_core callback

From: Hou Zhiqiang Release the secondary cores through the PSCI request. Signed-off-by: Hou Zhiqiang --- V3: - No change. drivers/cpu/imx8_cpu.c | 24 1 file changed, 24 insertions(+) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index c1315cc32dd..85

[PATCHv3 08/12] cmd: cpu: add release subcommand

From: Hou Zhiqiang Add a new subcommand 'release' to bring up a core to run baremetal and RTOS applications. For example on i.MX8M Plus EVK, release the LAST core to run a RTOS application, passing the sequence number of the CPU core to release, here it is 3: u-boot=> cpu list 0: cpu@0

[PATCHv3 06/12] cpu: imx: Add i.MX 8M series SoCs

From: Hou Zhiqiang Add i.MX 8M Mini, Nano and Plus SoCs support. Signed-off-by: Hou Zhiqiang --- V3: - No change. drivers/cpu/imx8_cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 6a97b7b9ad0..c1315cc32dd 100644 --- a/drive

[PATCHv3 05/12] cpu: imx: fix the CPU type field width

From: Hou Zhiqiang Increase one more bit to cover all CPU types. Otherwise it shows wrong CPU info on some platforms, such as i.MX8M Plus: U-Boot 2024.04+g674440bc73e+p0 (Jun 06 2024 - 10:05:34 +) CPU: NXP i.MX8MM Rev1.1 A53 at 4154504685 MHz at 30C Model: NXP i.MX8MPlus LPDD

[PATCHv3 04/12] cpu: imx: fix the CPU frequency in cpu_imx_get_info()

From: Hou Zhiqiang 1MHz = 100Hzz Signed-off-by: Hou Zhiqiang --- V3: - New patch. drivers/cpu/imx8_cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 4781a565547..601a7071a64 100644 --- a/drivers/cpu/imx

[PATCHv3 03/12] test: cpu: add test for release CPU core.

From: Hou Zhiqiang Add test for API cpu_release_core(). Signed-off-by: Hou Zhiqiang --- V3: - No change. test/dm/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/test/dm/cpu.c b/test/dm/cpu.c index acba8105996..8af25316cea 100644 --- a/test/dm/cpu.c +++ b/test/dm/cpu.c @@ -43,6 +4

[PATCHv3 02/12] cpu: sandbox: implement release_core callback

From: Hou Zhiqiang Add empty release CPU core function for testing. Signed-off-by: Hou Zhiqiang --- V3: - No change. drivers/cpu/cpu_sandbox.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/cpu/cpu_sandbox.c b/drivers/cpu/cpu_sandbox.c index e65e1bdc51b..b1527957831 100644

[PATCHv3 01/12] cpu: add release_core callback

From: Hou Zhiqiang Add a new callback release_core to the cpu_ops, which is used to release a CPU core to run baremetal or RTOS application on a SoC with multiple CPU cores. Signed-off-by: Hou Zhiqiang --- V3: - No change. drivers/cpu/cpu-uclass.c | 10 ++ include/cpu.h|

[PATCHv3 0/12] Add a subcommand 'release' to cmd/cpu.c

From: Hou Zhiqiang This patch set is to add a subcommand 'release' to the 'cpu' command in cmd/cpu.c, making the command is able to release a core to run baremetal and RTOS applications. Fixed some problems of the imx8_cpu.c and added i.MX 8M series SoCs support. And enabled the 'cpu' command a

[PATCHv2] clk: imx8m: register ARM A53 core clock

From: Hou Zhiqiang Register ARM A53 core clock for i.MX 8M Mini, Nano and Plus. Signed-off-by: Hou Zhiqiang --- V2: - Fixed the change log: s/A55/A53 drivers/clk/imx/clk-imx8mm.c | 6 ++ drivers/clk/imx/clk-imx8mn.c | 7 +++ drivers/clk/imx/clk-imx8mp.c | 7 +++ 3 files changed,

[PATCHv2 9/9] configs: imx93: enable the 'cpu' command

From: Hou Zhiqiang Enable the 'cpu' command to display the CPU info and release CPU core to run baremetal or RTOS applications. Signed-off-by: Hou Zhiqiang --- V2: - No change. configs/imx93_11x11_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx93_11x11_evk_defco

[PATCHv2 8/9] configs: imx8m: enable the 'cpu' command

From: Hou Zhiqiang Enable the 'cpu' command and the depended imx CPU driver to display the CPU info and release CPU core to run baremetal or RTOS applications. Signed-off-by: Hou Zhiqiang --- V2: - No change. configs/imx8mm_evk_defconfig | 3 +++ configs/imx8mn_evk_defconfig | 3 +++ configs

[PATCHv2 7/9] cmd: cpu: add release subcommand

From: Hou Zhiqiang Add a new subcommand 'release' to bring up a core to run baremetal and RTOS applications. For example on i.MX8M Plus EVK, release the LAST core to run a RTOS application, passing the sequence number of the CPU core to release, here it is 3: u-boot=> cpu list 0: cpu@0

[PATCHv2 6/9] cpu: imx: Add i.MX 8M series SoCs

From: Hou Zhiqiang Add i.MX 8M Mini, Nano and Plus SoCs support. Signed-off-by: Hou Zhiqiang --- V2: - New patch. drivers/cpu/imx8_cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 0509becf91e..dfedc9ffd14 100644 --- a/drive

[PATCHv2 5/9] cpu: imx: fix the CPU type field width

From: Hou Zhiqiang Increase one more bit to cover all CPU types. Otherwise it shows wrong CPU info on some platforms, such as i.MX8M Plus: U-Boot 2024.04+g674440bc73e+p0 (Jun 06 2024 - 10:05:34 +) CPU: NXP i.MX8MM Rev1.1 A53 at 4154504685 MHz at 30C Model: NXP i.MX8MPlus LPDD

[PATCHv2 4/9] cpu: imx: implement release_core callback

From: Hou Zhiqiang Release the secondary cores through the PSCI request. Signed-off-by: Hou Zhiqiang --- V2: - No change. drivers/cpu/imx8_cpu.c | 26 +- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c inde

[PATCHv2 3/9] test: cpu: add test for release CPU core.

From: Hou Zhiqiang Add test for API cpu_release_core(). Signed-off-by: Hou Zhiqiang --- V2: - New patch. test/dm/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/test/dm/cpu.c b/test/dm/cpu.c index acba8105996..8af25316cea 100644 --- a/test/dm/cpu.c +++ b/test/dm/cpu.c @@ -43,6 +4

[PATCHv2 2/9] cpu: sandbox: implement release_core callback

From: Hou Zhiqiang Add empty release CPU core function for testing. Signed-off-by: Hou Zhiqiang --- V2: - New patch. drivers/cpu/cpu_sandbox.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/cpu/cpu_sandbox.c b/drivers/cpu/cpu_sandbox.c index e65e1bdc51b..b1527957831 100644

[PATCHv2 1/9] cpu: add release_core callback

From: Hou Zhiqiang Add a new callback release_core to the cpu_ops, which is used to release a CPU core to run baremetal or RTOS application on a SoC with multiple CPU cores. Signed-off-by: Hou Zhiqiang --- V2: - No change. drivers/cpu/cpu-uclass.c | 10 ++ include/cpu.h|

[PATCHv2 0/9] Add a subcommand 'release' to cmd/cpu.c

From: Hou Zhiqiang This patch set is to add a subcommand 'release' to the 'cpu' command in cmd/cpu.c, making the command is able to release a core to run baremetal and RTOS applications. And enabled the 'cpu' command and imx CPU driver for i.MX 8M series EVK boards and i.MX 93 EVK board. depend

[PATCH] clk: imx8m: register ARM A55 core clock

From: Hou Zhiqiang Register ARM A55 core clock for i.MX 8M Mini, Nano and Plus. Signed-off-by: Hou Zhiqiang --- drivers/clk/imx/clk-imx8mm.c | 6 ++ drivers/clk/imx/clk-imx8mn.c | 7 +++ drivers/clk/imx/clk-imx8mp.c | 7 +++ 3 files changed, 20 insertions(+) diff --git a/drivers/c

[PATCH] clk: fix ccf_clk_get_rate

From: Hou Zhiqiang As the type of return value is 'ulong', when clk_get_by_id() failed, it should return 0 to indicate the get_rate operation doesn't succeed. Signed-off-by: Hou Zhiqiang --- drivers/clk/clk.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk

[PATCHv1 1/5] cpu: add release_core callback

From: Hou Zhiqiang Add a new callback release_core to the cpu_ops, which is used to release a CPU core to run baremetal or RTOS application on a SoC with multiple CPU cores. Signed-off-by: Hou Zhiqiang --- drivers/cpu/cpu-uclass.c | 10 ++ include/cpu.h| 15 +++

[PATCHv1 3/5] cmd: cpu: add release subcommand

From: Hou Zhiqiang Add a new subcommand 'release' to bring up a core to run baremetal and RTOS applications. For example on i.MX8M Plus EVK, release the LAST core to run a RTOS application, passing the sequence number of the CPU core to release, here it is 3: u-boot=> cpu list 0: cpu@0

[PATCHv1 5/5] configs: imx93: enable the 'cpu' command

From: Hou Zhiqiang Enable the 'cpu' command to display the CPU info and release CPU core to run baremetal or RTOS applications. Signed-off-by: Hou Zhiqiang --- configs/imx93_11x11_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx

[PATCHv1 4/5] configs: imx8m: enable the 'cpu' command

From: Hou Zhiqiang Enable the 'cpu' command and the depended imx CPU driver to display the CPU info and release CPU core to run baremetal or RTOS applications. Signed-off-by: Hou Zhiqiang --- configs/imx8mm_evk_defconfig | 3 +++ configs/imx8mn_evk_defconfig | 3 +++ configs/imx8mp_evk_defconf

[PATCHv1 2/5] cpu: imx: implement release_core callback

From: Hou Zhiqiang Release the secondary cores through the PSCI request. Signed-off-by: Hou Zhiqiang --- drivers/cpu/imx8_cpu.c | 26 +- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 4781a56554..5942a

[PATCHv1 0/5] Add a subcommand 'release' to cmd/cpu.c

From: Hou Zhiqiang This patch set is to add a subcommand 'release' to the 'cpu' command in cmd/cpu.c, making the command is able to release a core to run baremetal and RTOS applications. And enabled the 'cpu' command and imx CPU driver for i.MX 8M series EVK boards and i.MX 93 EVK board. Hou Zh

[PATCHv1 3/3] configs: imx93-11x11-evk: enable CONFIG_MP to support cpu command

From: Tao Yang Enable the cpu command support for the default config. Signed-off-by: Tao Yang Signed-off-by: Hou Zhiqiang --- configs/imx93_11x11_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 2246

[PATCHv1 2/3] imx93_evk: add definition MAX_CPUS

From: Tao Yang Add definition for determining the implemented CPU numbers. Signed-off-by: Tao Yang Signed-off-by: Hou Zhiqiang --- include/configs/imx93_evk.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index

[PATCHv1 1/3] mp: imx9: add cpu command support

From: Tao Yang Implement the cpu command to kick cpu core to run barematel or RTOS applications. Signed-off-by: Tao Yang Signed-off-by: Hou Zhiqiang --- arch/arm/mach-imx/imx9/Makefile | 4 +- arch/arm/mach-imx/imx9/mp.c | 81 + 2 files changed, 84 inserti

[PATCHv1 0/3] Enable the 'cpu' command for i.MX93 EVK board

From: Hou Zhiqiang This patch set is to enable the 'cpu' command for i.MX93 EVK, so that it can kick one CPU core to run the barematel or RTOS applicatons under U-Boot. Tao Yang (3): mp: imx9: add cpu command support imx93_evk: add definition CONFIG_MAX_CPUS configs: imx93-11x11-evk: enabl

[PATCHv1 1/2] mp: imx8m: add cpu command support

From: Hou Zhiqiang Implement the cpu command to kick cpu core to run barematel or RTOS applications. Signed-off-by: Hou Zhiqiang Signed-off-by: Yi Zhao Signed-off-by: Jiafei Pan --- arch/arm/mach-imx/imx8m/Makefile | 3 +- arch/arm/mach-imx/imx8m/mp.c | 100

[PATCHv1 2/2] mp: imx8m: enable CONFIG_MP to support cpu command

From: Jiafei Pan Enable the cpu command support for the default config. Signed-off-by: Jiafei Pan Signed-off-by: Hou Zhiqiang --- configs/imx8mm_evk_defconfig | 1 + configs/imx8mn_ddr4_evk_defconfig | 1 + configs/imx8mp_evk_defconfig | 1 + 3 files changed, 3 insertions(+) diff -

[PATCHv1 0/2] Enable the 'cpu' command for i.MX8M series EVK boards

From: Hou Zhiqiang This patch set is to enable the 'cpu' command for i.MX8M Plus, Mini and Nano EVK, so that it can kick one CPU core to run the barematel or RTOS applicatons under U-Boot. Hou Zhiqiang (1): mp: imx8m: add cpu command support Jiafei Pan (1): mp: imx8m: enable CONFIG_MP to su

[PATCH] arch: arm: recode the initialization of GICv3 ITS Re-Distributor tables

From: Hou Zhiqiang The current implementation needs the caller provides the memory region for the property and pending tables and the number of re-distibutor, and it doesn't handle the address alignment of the tables and doesn't help to add the reserved-memory node for the tables. This patch cha

[PATCH] tools: pblimage: fix image header verification function

From: Hou Zhiqiang The Layerscape platforms have different RCW header value from FSL PowerPC platforms, the current image header verification callback is only working on PowerPC, it will fail on Layerscape, this patch is to fix this issue. This is a historical problem and exposed by the followin

[PATCH] checkpatch: report ERROR only on disabling of fdt and initrd relocation

From: Hou Zhiqiang Let the check pass when patches have these patterns in their context. Signed-off-by: Hou Zhiqiang --- scripts/checkpatch.pl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index 5696d3a5f3..cf59e2bb70 100755 -

[PATCHv2] pci: layerscape: update the searching compatible of LX2160A PCIe

From: Hou Zhiqiang The current fixup of LX2160A PCIe nodes is based on non-production rev1 silicon, and in Linux the nodes have been updated for rev2 silicon, so update the searching compatible string to match the kernel changes. And for compatibility with the rev1 nodes, move forward the board s

[PATCH] pci: layerscape: update the searching compatible of LX2160A PCIe

From: Hou Zhiqiang The current fixup of LX2160A PCIe nodes is based on non-production rev1 silicon, and in Linux the nodes have been updated for rev2 silicon, so update the searching compatible string to match the kernel changes. And for compatibility with the rev1 nodes, move forward the board s

[PATCHv2] pci: layerscape: Fix the LUT and msi-map mismatch issue

From: Hou Zhiqiang In the current code, it doesn't reset the cursors of LUT entry and StreamID at the beginning of the fixup, so it can result in LUT entry setup and msi-map mismatch and LUT entries and StreamID leaking when reload and fixup the DTB. This patch move the initialization of LUT entr

[PATCH] pci: layerscape: Fix the LUT and msi-map mismatch issue

From: Hou Zhiqiang In the current code, it doesn't reset the cursors of LUT entry and StreamID at the beginning of the fixup, so it can result in LUT entry setup and msi-map mismatch and LUT entries and StreamID leaking when reload and fixup the DTB. This patch move the initialization of LUT entr

[PATCHv2] configs: Layerscape: Remove the 'fdt_addr' env

From: Hou Zhiqiang On Layerscape platforms, the DTB is loaded from boot filesystem, per the fdt_addr description in doc/README.distro, it must be removed. Signed-off-by: Hou Zhiqiang --- V2: - Removed unrelated description in change log. include/configs/ls1012a2g5rdb.h | 1 - include/config

[PATCH] configs: Layerscape: Remove the 'fdt_addr' env

From: Hou Zhiqiang On Layerscape platforms, the DTB is loaded from boot filesystem, per the fdt_addr description in doc/README.distro, it must be removed. And on many platforms, like ls1046a, ls1088a, ls2088a and lx216xa, the 'fdt_addr' pointed address is not accessible. And with the current EFI

[PATCH] configs: layerscape: Disable the EFI_LOADER feature

From: Hou Zhiqiang The feature BOOTENV_SHARED_EFI is not supported on layerscape boards, it didn't result kernel boot crash previously since there isn't the efi/boot/"BOOTEFI_NAME" and it skip calling of 'boot_efi_binary'. But since the commit f3866909e350 ("distro_bootcmd: call EFI bootmgr even

[PATCH] net: fm: Fix a memory leak issue

From: Hou Zhiqiang Fix a memory leak issue in the RX port initialization. Signed-off-by: Hou Zhiqiang --- drivers/net/fm/eth.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 0e89e663f7..7c23ccc1f0 100644 --- a/drivers/ne

[PATCH] net: e1000: Fix Unchecked return value coverity

From: Hou Zhiqiang Added check for return value of e1000_read_phy_reg(). Signed-off-by: Hou Zhiqiang --- drivers/net/e1000.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 694114eca7..1f0d559415 100644 --- a/driv

[PATCH] pci: layerscape: Change to allocate zeroed memery for struct ls_pcie

From: Hou Zhiqiang As on some incipient Layerscape platforms (LS1043A series) there isn't separate PF control register block, these registers reside in the LUT register block, so when the driver detected there isn't 'ctrl', it will assign the 'lut' address to the ls_pcie->ctrl. The current code

[PATCHv3] arm64: gic-v3-its: Clear the Pending table before enabling LPIs

From: Hou Zhiqiang The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables must contain only zeros on initial allocation, and this must be visible to the Redistributors, or else the effect is UNPREDICTABLE". And as the following statement, we here clear the whole Pending tables

[PATCHv2] arm64: gic-v3-its: Clear the Pending table before enabling LPIs

From: Hou Zhiqiang The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables must contain only zeros on initial allocation, and this must be visible to the Redistributors, or else the effect is UNPREDICTABLE". And as the following statement, we here clear the whole Pending tables

[PATCH] arm64: gic-v3-its: Clear the Pending talbe before enabling LPIs

From: Hou Zhiqiang The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables must contain only zeros on initial allocation, and this must be visible to the Redistributors, or else the effect is UNPREDICTABLE". And as the following statement, we here clear the whole Pending talbes

[PATCH] configs: T1042: Drop the CONFIG_VIDEO

From: Hou Zhiqiang Drop the CONFIG_VIDEO to fix the following build warning. = WARNING == This board does not use CONFIG_DM_VIDEO Please update the board to use CONFIG_DM_VIDEO before the v2019.07 release. UPD include/generated/dt.h Failure to update by

[PATCH] armv7: ls102xa: Enable I-Cache to speed up the boot time

From: Hou Zhiqiang Enable the I-Cache to speed up the boot time, especailly for the NOR boot, currently it takes about 15 seconds from power up to the U-Boot prompt, and with the I-Cache enabled it only takes around 2.5 seconds. Signed-off-by: Hou Zhiqiang --- arch/arm/cpu/armv7/ls102xa/cpu.c

[PATCH] pci: kconfig: layerscape: Change LX2162A PCIe node compatible string

From: Hou Zhiqiang LX2162A is not like LX2160A which has different PCIe controller in rev1 and rev2 silicon. It supports only one configuration of PCIe controller, which is same as LS2088A. So update PCIe compatible string same as LS2088A. Signed-off-by: Hou Zhiqiang --- drivers/pci/Kconfig |

[PATCHv2] pci: layerscape: Remove the shadow SVR definitions

From: Hou Zhiqiang This patch moves the SVR definitions to a new svr.h for Layerscape armv7 and armv8 platforms respectively, so that the PCIe driver can reuse them. Signed-off-by: Hou Zhiqiang --- V2: - rebase the patch and correct the typos in the subject .../arm/include/asm/arch-fsl-layer

[PATCH] pci: layerscape: fix a dead loop issue

From: Hou Zhiqiang The commit 8ec619f8fd84 added the PCIe EP nodes fixup of LX2160A, but it didn't update the condition value when there isn't a property 'apio-wins'. Fixes: 8ec619f8fd84 ("pci: layerscape: Fixup PCIe EP mode DT nodes for LX2160A rev2") Signed-off-by: Hou Zhiqiang --- drivers/

[PATCH] dm: pci: fsl: Correct the workaround of erratum A-007815

From: Hou Zhiqiang The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang --- drivers/pci/pcie_fsl.c | 20 drivers/pci/pcie_fsl.h | 2 ++ 2 f

[PATCHv2] pci: layerscape: Fixup PCIe EP mode DT nodes for LX2160A rev2

From: Hou Zhiqiang LX2160A rev2 uses different PCIe controller, so EP mode DT nodes also need to be fixed up. Signed-off-by: Hou Zhiqiang --- V2: - Fix a dead loop issue. drivers/pci/pcie_layerscape_fixup_common.c | 28 ++ 1 file changed, 28 insertions(+) diff --git a/dr

[PATCHv6 16/18] dts: powerpc: p2020rdb: Add eTSEC DT nodes

From: Hou Zhiqiang P2020RDB implements 3 enhanced three-speed Ethernet controllers, and the connection is shown below: eTSEC1: Connected to RGMII switch VSC7385 eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY AR8021 Signed-off-by: Hou Zhiqiang --- V6: - No cha

[PATCHv6 13/18] dts: powerpc: p1010rdb: Add eTSEC DT nodes

From: Hou Zhiqiang P1010RDB implements 3 enhanced three-speed Ethernet controllers, and the connection is shown below: eTSEC1: Connected to RGMII PHY AR8033 eTSEC2: Connected to SGMII PHY AR8033 eTSEC3: Connected to SGMII PHY AR8033 Signed-off-by: Hou Zhiqiang --- V6: - No change.

[PATCHv6 15/18] configs: P1010RDB: Enable DM_ETH config

From: Hou Zhiqiang Enable the DM_ETH and DM_MDIO config. Signed-off-by: Hou Zhiqiang --- V6: - No change. configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_S

[PATCHv6 14/18] powerpc: p1010rdb: Compile legacy ethernet init function when no DM_ETH

From: Hou Zhiqiang The board_eth_init() is only used by legacy ethernet driver framework, so do not compile it when DM_ETH config has been selected. Signed-off-by: Hou Zhiqiang Reviewed-by: Vladimir Oltean --- V6: - No change. board/freescale/p1010rdb/p1010rdb.c | 2 ++ 1 file changed, 2 in

[PATCHv6 18/18] configs: enable DM_MDIO for LS1021A-TWR and LS1021A-TSN

From: Vladimir Oltean The tsec driver now requires DM_MDIO when DM_ETH is enabled. To avoid build errors, enable DM_MDIO in these boards' configs before we actually add DM_MDIO support to tsec. Signed-off-by: Vladimir Oltean Signed-off-by: Hou Zhiqiang --- V6: - No code change, just move it t

[PATCHv6 17/18] configs: P2020RDB: Enable DM_ETH config

From: Hou Zhiqiang Enable the DM_ETH and DM_MDIO config. On P2020RDB, the eTSEC1 is connecting with a switch VSC7385, so also enable the fixed PHY support. Signed-off-by: Hou Zhiqiang Reviewed-by: Vladimir Oltean --- V6: - No change. configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 +++ co

[PATCHv6 12/18] configs: P1020RDB: Enable DM_ETH config

From: Hou Zhiqiang Enable the DM_ETH and DM_MDIO config. On P1020RDB, the eTSEC1 is connecting with a switch VSC7385, so also enable the fixed PHY support. Signed-off-by: Hou Zhiqiang --- V6: - No change. configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 +++ configs/P1020RDB-PC_36BIT_SDCARD

[PATCHv6 04/18] net: tsec: convert to use DM_MDIO when DM_ETH enabled

From: Hou Zhiqiang For the platforms on which the eTSEC driver uses DM_ETH, convert its MDIO controller code to also use DM_MDIO. Note that for handling the TBI PHY (the MAC PCS for SGMII), we still don't register a udevice for it, since we can drive it locally and there is no point in doing oth

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