[U-Boot] [usb] dwc3 -- phy -- hub: a hint/help/an idea needed.

Hi, Any ideas/hints needed with regard to dwc3 -- phy -- hub support on a custom board. I've been struggling with u-boot implementation of usb support on a mips32-based development board (a SoC with DWC3 integrated). SoC has the ULPI interface, and by means of it, it's connected to USB 2.0 phy

[U-Boot] [usb] dwc3 -- phy -- hub: a hint/help/an idea needed.

Hi, Any ideas/hints needed with regard to dwc3 -- phy -- hub support on a custom board. I've been struggling with u-boot implementation of usb support on a mips32-based development board (a SoC with DWC3 integrated). SoC has the ULPI interface, and by means of it, it's connected to USB 2.0 phy

[U-Boot] [mips, usb xhci] Question / advice needed: cacheable adresses as a device output buffers?

Is it possible to use *cached* addresses as device's output buffer? E.g, is it a correct thing, to read an uImage from USB pen to cacheable addresses in order to boot from these cached area? U-Boot 2014.10-00051-g8cb056b-dirty / SDK (May 15 2018 - 17:11:35) CPU: MIPS32 P5600 @ 1200 MHz (Rev

[U-Boot] [usb dwc3] xHCI driver -- a hint needed.

Hi, I've been trying to bring up a dwc3 usb controller included in 32-bit MIPS chip. Usb is the one port usb2.0 host module, compliant with xHCI Revision 1.0, UTMI+ Low Pin interface (ULPI) Revision 1.1 and AMBA AXI Protocol specification. g_snpsid register reports 0x5533290a revision. It's ve

[U-Boot] [powerpc NOR flash start address]

Hello, probably an obvious question, but nevertheless... More than a year ago, u-boot binary size was incfreased for powerpc boards (commit e222b1f36fedb0363dbc21e0add7dc3848bae553 "powerpc/mpc85xx:Increase binary size for P, B & T series boards."), so CONFIG_SYS_TEXT_BASE changed from 0xeff80